From: Daniel Palmer <daniel@0x0f.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux@armlinux.org.uk, arnd@arndb.de, afaerber@suse.de, maz@kernel.org, w@1wt.eu, Daniel Palmer <daniel@0x0f.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v5 07/12] ARM: mstar: Add binding details for mstar,l3bridge Date: Fri, 10 Jul 2020 18:45:39 +0900 [thread overview] Message-ID: <20200710094544.430258-8-daniel@0x0f.com> (raw) In-Reply-To: <20200710094544.430258-1-daniel@0x0f.com> This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../bindings/misc/mstar,l3bridge.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml new file mode 100644 index 000000000000..cb7fd1cdfb1a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com> To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, arnd@arndb.de, Rob Herring <robh@kernel.org>, maz@kernel.org, Daniel Palmer <daniel@0x0f.com>, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, robh+dt@kernel.org, w@1wt.eu, afaerber@suse.de Subject: [PATCH v5 07/12] ARM: mstar: Add binding details for mstar,l3bridge Date: Fri, 10 Jul 2020 18:45:39 +0900 [thread overview] Message-ID: <20200710094544.430258-8-daniel@0x0f.com> (raw) In-Reply-To: <20200710094544.430258-1-daniel@0x0f.com> This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../bindings/misc/mstar,l3bridge.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml new file mode 100644 index 000000000000..cb7fd1cdfb1a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-10 9:46 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-10 9:45 [PATCH v5 00/12] Initial MStar/Sigmastar ARMv7 SoC support Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 01/12] dt-bindings: vendor-prefixes: Add mstar vendor prefix Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 02/12] dt-bindings: vendor-prefixes: Add sstar " Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 03/12] dt-bindings: vendor-prefixes: Add 70mai " Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 04/12] dt-bindings: vendor-prefixes: Add thingy.jp prefix Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 05/12] dt-bindings: arm: Add mstar YAML schema Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 06/12] ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer [this message] 2020-07-10 9:45 ` [PATCH v5 07/12] ARM: mstar: Add binding details for mstar,l3bridge Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 08/12] ARM: mstar: Add Armv7 base dtsi Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 09/12] ARM: mstar: Add infinity/infinity3 family dtsis Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 10/12] ARM: mstar: Add mercury5 series dtsis Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 11/12] ARM: mstar: Add dts for msc313(e) based BreadBee boards Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-10 9:45 ` [PATCH v5 12/12] ARM: mstar: Add dts for 70mai midrive d08 Daniel Palmer 2020-07-10 9:45 ` Daniel Palmer 2020-07-24 14:37 ` [PATCH v5 00/12] Initial MStar/Sigmastar ARMv7 SoC support Arnd Bergmann 2020-07-24 14:37 ` Arnd Bergmann 2020-07-25 4:44 ` Daniel Palmer 2020-07-25 4:44 ` Daniel Palmer
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