From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 2/2] target/riscv: fix vector index load/store constraints Date: Tue, 21 Jul 2020 21:37:42 +0800 [thread overview] Message-ID: <20200721133742.2298-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200721133742.2298-1-zhiwei_liu@c-sky.com> Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 7b4752b911..887c6b8883 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } +/* + * For vector indexed segment loads, the destination vector register + * groups cannot overlap the source vector register group (specified by + * `vs2`), else an illegal instruction exception is raised. + */ static bool ld_index_check(DisasContext *s, arg_rnfvm* a) { return (vext_check_isa_ill(s) && vext_check_overlap_mask(s, a->rd, a->vm, false) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + vext_check_nf(s, a->nf) && + ((a->nf == 1) || + vext_check_overlap_group(a->rd, a->nf << s->lmul, + a->rs2, 1 << s->lmul))); } GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 2/2] target/riscv: fix vector index load/store constraints Date: Tue, 21 Jul 2020 21:37:42 +0800 [thread overview] Message-ID: <20200721133742.2298-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200721133742.2298-1-zhiwei_liu@c-sky.com> Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 7b4752b911..887c6b8883 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } +/* + * For vector indexed segment loads, the destination vector register + * groups cannot overlap the source vector register group (specified by + * `vs2`), else an illegal instruction exception is raised. + */ static bool ld_index_check(DisasContext *s, arg_rnfvm* a) { return (vext_check_isa_ill(s) && vext_check_overlap_mask(s, a->rd, a->vm, false) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + vext_check_nf(s, a->nf) && + ((a->nf == 1) || + vext_check_overlap_group(a->rd, a->nf << s->lmul, + a->rs2, 1 << s->lmul))); } GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -- 2.23.0
next prev parent reply other threads:[~2020-07-21 13:38 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-21 13:37 [PATCH 1/2] target/riscv: Quiet Coverity complains about vamo* LIU Zhiwei 2020-07-21 13:37 ` LIU Zhiwei 2020-07-21 13:37 ` LIU Zhiwei [this message] 2020-07-21 13:37 ` [PATCH 2/2] target/riscv: fix vector index load/store constraints LIU Zhiwei 2020-07-21 15:11 ` Alistair Francis 2020-07-21 15:11 ` Alistair Francis 2020-07-21 15:07 ` [PATCH 1/2] target/riscv: Quiet Coverity complains about vamo* Alistair Francis 2020-07-21 15:07 ` Alistair Francis 2020-07-21 15:30 ` Peter Maydell 2020-07-21 15:30 ` Peter Maydell 2020-07-22 16:40 ` Alistair Francis 2020-07-22 16:40 ` Alistair Francis
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200721133742.2298-2-zhiwei_liu@c-sky.com \ --to=zhiwei_liu@c-sky.com \ --cc=Alistair.Francis@wdc.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.