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From: Balbir Singh <sblbir@amazon.com>
To: <tglx@linutronix.de>, <linux-kernel@vger.kernel.org>
Cc: <jpoimboe@redhat.com>, <tony.luck@intel.com>,
	<keescook@chromium.org>, <benh@kernel.crashing.org>,
	<x86@kernel.org>, <dave.hansen@intel.com>,
	<thomas.lendacky@amd.com>, <torvalds@linux-foundation.org>,
	<mingo@kernel.org>, Balbir Singh <sblbir@amazon.com>
Subject: [PATCH v2 1/5] Add a per-cpu view of SMT state
Date: Wed, 29 Jul 2020 10:10:59 +1000	[thread overview]
Message-ID: <20200729001103.6450-2-sblbir@amazon.com> (raw)
In-Reply-To: <20200729001103.6450-1-sblbir@amazon.com>

A new field smt_active in cpuinfo_x86 identifies if the current core/cpu
is in SMT mode or not. This can be very helpful if the system has some
of its cores with threads offlined and can be used for cases where
action is taken based on the state of SMT. The follow up patches use
this feature.

Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Balbir Singh <sblbir@amazon.com>
---
 arch/x86/include/asm/processor.h |  2 ++
 arch/x86/kernel/smpboot.c        | 11 ++++++++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 03b7c4ca425a..23ea45dd6f14 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -136,6 +136,8 @@ struct cpuinfo_x86 {
 	u16			logical_die_id;
 	/* Index into per_cpu list: */
 	u16			cpu_index;
+	/*  Is SMT active on this core? */
+	bool			smt_active;
 	u32			microcode;
 	/* Address space bits used by the cache internally */
 	u8			x86_cache_bits;
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index ffbd9a3d78d8..0b12f24ebfbb 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -645,6 +645,9 @@ void set_cpu_sibling_map(int cpu)
 	threads = cpumask_weight(topology_sibling_cpumask(cpu));
 	if (threads > __max_smt_threads)
 		__max_smt_threads = threads;
+
+	for_each_cpu(i, topology_sibling_cpumask(cpu))
+		cpu_data(i).smt_active = threads > 1;
 }
 
 /* maps the cpu to the sched domain representing multi-core */
@@ -1557,10 +1560,16 @@ static void remove_siblinginfo(int cpu)
 
 	for_each_cpu(sibling, topology_die_cpumask(cpu))
 		cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
-	for_each_cpu(sibling, topology_sibling_cpumask(cpu))
+
+	for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
 		cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
+		if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
+			cpu_data(sibling).smt_active = false;
+	}
+
 	for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
 		cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
+
 	cpumask_clear(cpu_llc_shared_mask(cpu));
 	cpumask_clear(topology_sibling_cpumask(cpu));
 	cpumask_clear(topology_core_cpumask(cpu));
-- 
2.17.1


  reply	other threads:[~2020-07-29  0:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29  0:10 [PATCH v2 0/5] Implement optional L1D flushing for Balbir Singh
2020-07-29  0:10 ` Balbir Singh [this message]
2020-09-16 13:11   ` [tip: x86/pti] x86/smp: Add a per-cpu view of SMT state tip-bot2 for Balbir Singh
2020-07-29  0:11 ` [PATCH v2 2/5] x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-07-29  0:11 ` [PATCH v2 3/5] x86/mm: Optionally flush L1D on context switch Balbir Singh
2020-07-29  9:30   ` kernel test robot
2020-09-16 13:11   ` [tip: x86/pti] " tip-bot2 for Balbir Singh
2020-07-29  0:11 ` [PATCH v2 4/5] prctl: Hook L1D flushing in via prctl Balbir Singh
2020-07-29 13:14   ` Tom Lendacky
2020-07-30  0:13     ` Singh, Balbir
2020-07-29 20:13   ` kernel test robot
2020-09-16 13:11   ` [tip: x86/pti] " tip-bot2 for Balbir Singh
2020-07-29  0:11 ` [PATCH v2 5/5] Documentation: Add L1D flushing Documentation Balbir Singh
2020-09-16 13:11   ` [tip: x86/pti] " tip-bot2 for Balbir Singh

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