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From: Mohan Kumar <mkumard@nvidia.com>
To: <tiwai@suse.com>, <perex@perex.cz>
Cc: <alsa-devel@alsa-project.org>, <linux-tegra@vger.kernel.org>,
	<treding@nvidia.com>, <jonathanh@nvidia.com>, <spujar@nvidia.com>,
	Mohan Kumar <mkumard@nvidia.com>
Subject: [PATCH 1/3] ASoC: hda/tegra: Set buffer alignment to 128 bytes
Date: Wed, 5 Aug 2020 14:41:14 +0530	[thread overview]
Message-ID: <20200805091116.2314-2-mkumard@nvidia.com> (raw)
In-Reply-To: <20200805091116.2314-1-mkumard@nvidia.com>

Set  chip->align_buffer_size to 1 for Tegra platforms to make the buffer
alignment to be multiple of 128 bytes. This fix is applied as gstreamer
alsasink gets stuck with the default buffer-time and latency-time
parameters with 4 byte buffer alignment.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
---
 sound/pci/hda/hda_tegra.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c
index 5637f0129932..ecf98eb9df36 100644
--- a/sound/pci/hda/hda_tegra.c
+++ b/sound/pci/hda/hda_tegra.c
@@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
 	gcap = azx_readw(chip, GCAP);
 	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
 
+	chip->align_buffer_size = 1;
+
 	/* read number of streams from GCAP register instead of using
 	 * hardcoded value
 	 */
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Mohan Kumar <mkumard@nvidia.com>
To: <tiwai@suse.com>, <perex@perex.cz>
Cc: alsa-devel@alsa-project.org, spujar@nvidia.com,
	jonathanh@nvidia.com, linux-tegra@vger.kernel.org,
	treding@nvidia.com, Mohan Kumar <mkumard@nvidia.com>
Subject: [PATCH 1/3] ASoC: hda/tegra: Set buffer alignment to 128 bytes
Date: Wed, 5 Aug 2020 14:41:14 +0530	[thread overview]
Message-ID: <20200805091116.2314-2-mkumard@nvidia.com> (raw)
In-Reply-To: <20200805091116.2314-1-mkumard@nvidia.com>

Set  chip->align_buffer_size to 1 for Tegra platforms to make the buffer
alignment to be multiple of 128 bytes. This fix is applied as gstreamer
alsasink gets stuck with the default buffer-time and latency-time
parameters with 4 byte buffer alignment.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
---
 sound/pci/hda/hda_tegra.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c
index 5637f0129932..ecf98eb9df36 100644
--- a/sound/pci/hda/hda_tegra.c
+++ b/sound/pci/hda/hda_tegra.c
@@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
 	gcap = azx_readw(chip, GCAP);
 	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
 
+	chip->align_buffer_size = 1;
+
 	/* read number of streams from GCAP register instead of using
 	 * hardcoded value
 	 */
-- 
2.17.1


  reply	other threads:[~2020-08-05  9:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-05  9:11 [PATCH 0/3] Tegra Specific fixes Mohan Kumar
2020-08-05  9:11 ` Mohan Kumar
2020-08-05  9:11 ` Mohan Kumar [this message]
2020-08-05  9:11   ` [PATCH 1/3] ASoC: hda/tegra: Set buffer alignment to 128 bytes Mohan Kumar
2020-08-05  9:11 ` [PATCH 2/3] ALSA: hda: Add behaviour flag for dma stop delay Mohan Kumar
2020-08-05  9:11   ` Mohan Kumar
2020-08-05  9:29   ` Takashi Iwai
2020-08-05  9:29     ` Takashi Iwai
2020-08-05  9:11 ` [PATCH 3/3] ALSA: hda/tegra: Add 100us " Mohan Kumar
2020-08-05  9:11   ` Mohan Kumar

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