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From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, robh+dt@kernel.org,
	bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com,
	gustavo.pimentel@synopsys.com, roy.zang@nxp.com,
	jingoohan1@gmail.com, andrew.murray@arm.com
Cc: mingkai.hu@nxp.com, minghuan.Lian@nxp.com,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a
Date: Tue, 11 Aug 2020 17:54:39 +0800	[thread overview]
Message-ID: <20200811095441.7636-11-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20200811095441.7636-1-Zhiqiang.Hou@nxp.com>

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add PCIe EP node for ls1088a to support EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V7:
 - Rebase the patch without functionality change.

 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..915592141f1b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -499,6 +499,17 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3400000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03400000 0x0 0x00100000
+			       0x20 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <24>;
+			num-ob-windows = <128>;
+			max-functions = /bits/ 8 <2>;
+			status = "disabled";
+		};
+
 		pcie@3500000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
@@ -525,6 +536,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3500000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03500000 0x0 0x00100000
+			       0x28 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie@3600000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
@@ -551,6 +572,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3600000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03600000 0x0 0x00100000
+			       0x30 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		smmu: iommu@5000000 {
 			compatible = "arm,mmu-500";
 			reg = <0 0x5000000 0 0x800000>;
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, robh+dt@kernel.org,
	bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com,
	gustavo.pimentel@synopsys.com, roy.zang@nxp.com,
	jingoohan1@gmail.com, andrew.murray@arm.com
Cc: minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	mingkai.hu@nxp.com
Subject: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a
Date: Tue, 11 Aug 2020 17:54:39 +0800	[thread overview]
Message-ID: <20200811095441.7636-11-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20200811095441.7636-1-Zhiqiang.Hou@nxp.com>

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add PCIe EP node for ls1088a to support EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V7:
 - Rebase the patch without functionality change.

 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..915592141f1b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -499,6 +499,17 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3400000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03400000 0x0 0x00100000
+			       0x20 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <24>;
+			num-ob-windows = <128>;
+			max-functions = /bits/ 8 <2>;
+			status = "disabled";
+		};
+
 		pcie@3500000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
@@ -525,6 +536,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3500000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03500000 0x0 0x00100000
+			       0x28 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie@3600000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
@@ -551,6 +572,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3600000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03600000 0x0 0x00100000
+			       0x30 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		smmu: iommu@5000000 {
 			compatible = "arm,mmu-500";
 			reg = <0 0x5000000 0 0x800000>;
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, robh+dt@kernel.org,
	bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com,
	gustavo.pimentel@synopsys.com, roy.zang@nxp.com,
	jingoohan1@gmail.com, andrew.murray@arm.com
Cc: minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	mingkai.hu@nxp.com
Subject: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a
Date: Tue, 11 Aug 2020 17:54:39 +0800	[thread overview]
Message-ID: <20200811095441.7636-11-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20200811095441.7636-1-Zhiqiang.Hou@nxp.com>

From: Xiaowei Bao <xiaowei.bao@nxp.com>

Add PCIe EP node for ls1088a to support EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V7:
 - Rebase the patch without functionality change.

 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..915592141f1b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -499,6 +499,17 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3400000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03400000 0x0 0x00100000
+			       0x20 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <24>;
+			num-ob-windows = <128>;
+			max-functions = /bits/ 8 <2>;
+			status = "disabled";
+		};
+
 		pcie@3500000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
@@ -525,6 +536,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3500000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03500000 0x0 0x00100000
+			       0x28 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie@3600000 {
 			compatible = "fsl,ls1088a-pcie";
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
@@ -551,6 +572,16 @@
 			status = "disabled";
 		};
 
+		pcie_ep@3600000 {
+			compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+			reg = <0x00 0x03600000 0x0 0x00100000
+			       0x30 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ib-windows = <6>;
+			num-ob-windows = <8>;
+			status = "disabled";
+		};
+
 		smmu: iommu@5000000 {
 			compatible = "arm,mmu-500";
 			reg = <0 0x5000000 0 0x800000>;
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-08-11 10:02 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-11  9:54 [PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape Zhiqiang Hou
2020-08-11  9:54 ` Zhiqiang Hou
2020-08-11  9:54 ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 01/12] PCI: designware-ep: Add multiple PFs support for DWC Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-09-10 17:58   ` Rob Herring
2020-09-10 17:58     ` Rob Herring
2020-09-10 17:58     ` Rob Herring
2020-09-13 16:28     ` Z.q. Hou
2020-09-13 16:28       ` Z.q. Hou
2020-09-13 16:28       ` Z.q. Hou
2020-08-11  9:54 ` [PATCHv7 03/12] PCI: designware-ep: Move the function of getting MSI capability forward Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 04/12] PCI: designware-ep: Modify MSI and MSIX CAP way of finding Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-09-10 18:10   ` Rob Herring
2020-09-10 18:10     ` Rob Herring
2020-09-10 18:10     ` Rob Herring
2020-09-13 17:24     ` Z.q. Hou
2020-09-13 17:24       ` Z.q. Hou
2020-09-13 17:24       ` Z.q. Hou
2020-09-18  8:15     ` Z.q. Hou
2020-09-18  8:15       ` Z.q. Hou
2020-09-18  8:15       ` Z.q. Hou
2020-08-11  9:54 ` [PATCHv7 05/12] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 06/12] PCI: layerscape: Fix some format issue of the code Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 07/12] PCI: layerscape: Modify the way of getting capability with different PEX Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 08/12] PCI: layerscape: Modify the MSIX to the doorbell mode Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 09/12] PCI: layerscape: Add EP mode support for ls1088a and ls2088a Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` Zhiqiang Hou [this message]
2020-08-11  9:54   ` [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-09-10 16:47   ` Rob Herring
2020-09-10 16:47     ` Rob Herring
2020-09-10 16:47     ` Rob Herring
2020-09-13 16:26     ` Z.q. Hou
2020-09-13 16:26       ` Z.q. Hou
2020-09-13 16:26       ` Z.q. Hou
2020-08-11  9:54 ` [PATCHv7 11/12] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54 ` [PATCHv7 12/12] misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-08-11  9:54   ` Zhiqiang Hou
2020-09-10 18:17   ` Rob Herring
2020-09-10 18:17     ` Rob Herring
2020-09-10 18:17     ` Rob Herring
2020-09-13 17:24     ` Z.q. Hou
2020-09-13 17:24       ` Z.q. Hou
2020-09-13 17:24       ` Z.q. Hou
2020-09-17 16:20 ` [PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape Lorenzo Pieralisi
2020-09-17 16:20   ` Lorenzo Pieralisi
2020-09-17 16:20   ` Lorenzo Pieralisi
2020-09-18  2:55   ` Z.q. Hou
2020-09-18  2:55     ` Z.q. Hou
2020-09-18  2:55     ` Z.q. Hou

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