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From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, Andy Gross <agross@kernel.org>,
	Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Dilip Kota <eswara.kota@linux.intel.com>,
	Fabio Estevam <festevam@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Jonathan Chocron <jonnyc@amazon.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kukjin Kim <kgene@kernel.org>,
	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Shawn Guo <shawnguo@kernel.org>, Shawn Guo <shawn.guo@linaro.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Yue Wang <yue.wang@Amlogic.com>, Marc Zyngier <maz@kernel.org>,
	linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
	linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
Date: Thu, 20 Aug 2020 21:54:17 -0600	[thread overview]
Message-ID: <20200821035420.380495-38-robh@kernel.org> (raw)
In-Reply-To: <20200821035420.380495-1-robh@kernel.org>

The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so
let's retrieve it there and avoid storing the offset.

Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 6b102197a1b6..807e1fa1bd6f 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -72,7 +72,6 @@ struct intel_pcie_port {
 	struct clk		*core_clk;
 	struct reset_control	*core_rst;
 	struct phy		*phy;
-	u8			pcie_cap_ofst;
 };
 
 static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
@@ -132,7 +131,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp)
 static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
 {
 	u32 val;
-	u8 offset = lpp->pcie_cap_ofst;
+	u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
 
 	val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCAP);
 	lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
@@ -328,7 +327,6 @@ static void intel_pcie_turn_off(struct intel_pcie_port *lpp)
 
 static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 {
-	struct device *dev = lpp->pci.dev;
 	int ret;
 
 	intel_pcie_core_rst_assert(lpp);
@@ -346,17 +344,6 @@ static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 		goto clk_err;
 	}
 
-	if (!lpp->pcie_cap_ofst) {
-		ret = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
-		if (!ret) {
-			ret = -ENXIO;
-			dev_err(dev, "Invalid PCIe capability offset\n");
-			goto app_init_err;
-		}
-
-		lpp->pcie_cap_ofst = ret;
-	}
-
 	intel_pcie_rc_setup(lpp);
 	ret = intel_pcie_app_logic_setup(lpp);
 	if (ret)
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	linux-pci@vger.kernel.org,
	Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	linux-arm-kernel@axis.com, Jonathan Chocron <jonnyc@amazon.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Fabio Estevam <festevam@gmail.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Marc Zyngier <maz@kernel.org>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	linux-samsung-soc@vger.kernel.org,
	Dilip Kota <eswara.kota@linux.intel.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Kukjin Kim <kgene@kernel.org>, NXP Linux Team <linux-imx@nxp.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-arm-msm@vger.kernel.org,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Yue Wang <yue.wang@Amlogic.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	linux-tegra@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Jingoo Han <jingoohan1@gmail.com>, Andy Gross <agross@kernel.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Shawn Guo <shawn.guo@linaro.org>, Shawn Guo <shawnguo@kernel.org>,
	Lucas Stach <l.stach@pengutronix.de>
Subject: [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
Date: Thu, 20 Aug 2020 21:54:17 -0600	[thread overview]
Message-ID: <20200821035420.380495-38-robh@kernel.org> (raw)
In-Reply-To: <20200821035420.380495-1-robh@kernel.org>

The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so
let's retrieve it there and avoid storing the offset.

Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 6b102197a1b6..807e1fa1bd6f 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -72,7 +72,6 @@ struct intel_pcie_port {
 	struct clk		*core_clk;
 	struct reset_control	*core_rst;
 	struct phy		*phy;
-	u8			pcie_cap_ofst;
 };
 
 static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
@@ -132,7 +131,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp)
 static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
 {
 	u32 val;
-	u8 offset = lpp->pcie_cap_ofst;
+	u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
 
 	val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCAP);
 	lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
@@ -328,7 +327,6 @@ static void intel_pcie_turn_off(struct intel_pcie_port *lpp)
 
 static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 {
-	struct device *dev = lpp->pci.dev;
 	int ret;
 
 	intel_pcie_core_rst_assert(lpp);
@@ -346,17 +344,6 @@ static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 		goto clk_err;
 	}
 
-	if (!lpp->pcie_cap_ofst) {
-		ret = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
-		if (!ret) {
-			ret = -ENXIO;
-			dev_err(dev, "Invalid PCIe capability offset\n");
-			goto app_init_err;
-		}
-
-		lpp->pcie_cap_ofst = ret;
-	}
-
 	intel_pcie_rc_setup(lpp);
 	ret = intel_pcie_app_logic_setup(lpp);
 	if (ret)
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	linux-pci@vger.kernel.org,
	Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	linux-arm-kernel@axis.com, Jonathan Chocron <jonnyc@amazon.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Fabio Estevam <festevam@gmail.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Marc Zyngier <maz@kernel.org>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	linux-samsung-soc@vger.kernel.org,
	Dilip Kota <eswara.kota@linux.intel.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Kukjin Kim <kgene@kernel.org>, NXP Linux Team <linux-imx@nxp.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-arm-msm@vger.kernel.org,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Yue Wang <yue.wang@Amlogic.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	linux-tegra@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Jingoo Han <jingoohan1@gmail.com>, Andy Gross <agross@kernel.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Shawn Guo <shawn.guo@linaro.org>, Shawn Guo <shawnguo@kernel.org>,
	Lucas Stach <l.stach@pengutronix.de>
Subject: [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
Date: Thu, 20 Aug 2020 21:54:17 -0600	[thread overview]
Message-ID: <20200821035420.380495-38-robh@kernel.org> (raw)
In-Reply-To: <20200821035420.380495-1-robh@kernel.org>

The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so
let's retrieve it there and avoid storing the offset.

Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 6b102197a1b6..807e1fa1bd6f 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -72,7 +72,6 @@ struct intel_pcie_port {
 	struct clk		*core_clk;
 	struct reset_control	*core_rst;
 	struct phy		*phy;
-	u8			pcie_cap_ofst;
 };
 
 static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
@@ -132,7 +131,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp)
 static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
 {
 	u32 val;
-	u8 offset = lpp->pcie_cap_ofst;
+	u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
 
 	val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCAP);
 	lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
@@ -328,7 +327,6 @@ static void intel_pcie_turn_off(struct intel_pcie_port *lpp)
 
 static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 {
-	struct device *dev = lpp->pci.dev;
 	int ret;
 
 	intel_pcie_core_rst_assert(lpp);
@@ -346,17 +344,6 @@ static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
 		goto clk_err;
 	}
 
-	if (!lpp->pcie_cap_ofst) {
-		ret = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
-		if (!ret) {
-			ret = -ENXIO;
-			dev_err(dev, "Invalid PCIe capability offset\n");
-			goto app_init_err;
-		}
-
-		lpp->pcie_cap_ofst = ret;
-	}
-
 	intel_pcie_rc_setup(lpp);
 	ret = intel_pcie_app_logic_setup(lpp);
 	if (ret)
-- 
2.25.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

  parent reply	other threads:[~2020-08-21  3:57 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21  3:53 [PATCH v2 00/40] PCI: dwc: Driver clean-ups Rob Herring
2020-08-21  3:53 ` Rob Herring
2020-08-21  3:53 ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 01/40] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 02/40] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2021-08-08 15:13   ` Vidya Sagar
2021-08-08 15:13     ` Vidya Sagar
2021-08-08 15:13     ` Vidya Sagar
2021-08-09 14:52     ` Rob Herring
2021-08-09 14:52       ` Rob Herring
2021-08-09 14:52       ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 04/40] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 05/40] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 06/40] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 07/40] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-24 14:04   ` kernel test robot
2020-08-21  3:53 ` [PATCH v2 08/40] PCI: dwc: meson: " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 09/40] PCI: dwc: kirin: " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 10/40] PCI: dwc: exynos: " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 11/40] PCI: dwc: histb: " Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 12/40] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 13/40] PCI: dwc: Use generic config accessors Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 14/40] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 15/40] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 16/40] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 17/40] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 19/40] PCI: dwc: Simplify config space handling Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:53   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 20/40] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 21/40] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 23/40] PCI: dwc: Add a 'num_lanes' field to struct dw_pcie Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 24/40] PCI: dwc: Ensure FAST_LINK_MODE is cleared Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 26/40] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 27/40] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 28/40] PCI: dwc/imx6: Use common PCI register definitions Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 29/40] PCI: dwc/qcom: " Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 31/40] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 32/40] PCI: dwc: Remove read_dbi2 code Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 33/40] PCI: dwc: Make ATU accessors private Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 34/40] PCI: dwc: Centralize link gen setting Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 35/40] PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 36/40] PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` Rob Herring [this message]
2020-08-21  3:54   ` [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 38/40] PCI: dwc/intel-gw: Drop unused max_width Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 39/40] PCI: dwc: Move N_FTS setup to common setup Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2021-08-08 15:01   ` Vidya Sagar
2021-08-08 15:01     ` Vidya Sagar
2021-08-08 15:01     ` Vidya Sagar
2021-08-09 15:02     ` Rob Herring
2021-08-09 15:02       ` Rob Herring
2021-08-09 15:02       ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 40/40] PCI: dwc: Use DBI accessors Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-08-21  3:54   ` Rob Herring
2020-09-07  9:35 ` [PATCH v2 00/40] PCI: dwc: Driver clean-ups Lorenzo Pieralisi
2020-09-07  9:35   ` Lorenzo Pieralisi
2020-09-07  9:35   ` Lorenzo Pieralisi
2020-09-15  9:12 ` Michael Walle
2020-09-15  9:12   ` Michael Walle
2020-09-15  9:12   ` Michael Walle
2020-09-15 22:02   ` Rob Herring
2020-09-15 22:02     ` Rob Herring
2020-09-15 22:02     ` Rob Herring
2020-09-16  7:54     ` Michael Walle
2020-09-16  7:54       ` Michael Walle
2020-09-16  7:54       ` Michael Walle
2020-09-29  5:23       ` Kishon Vijay Abraham I
2020-09-29  5:23         ` Kishon Vijay Abraham I
2020-09-29  5:23         ` Kishon Vijay Abraham I
2020-09-29 14:32         ` Rob Herring
2020-09-29 14:32           ` Rob Herring
2020-09-29 14:32           ` Rob Herring

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