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From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [cip-dev] [PATCH 21/36] pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
Date: Fri, 21 Aug 2020 10:42:57 +0100	[thread overview]
Message-ID: <20200821094312.3249-22-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com>

[-- Attachment #1: Type: text/plain, Size: 4593 bytes --]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 99fdb920f5534d1c2f4b30c12eca4224ea260198 upstream.

Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in
pin definitions for the VIN5 channel.

This reduces kernel size by 240 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 90 ++++++++--------------------
 1 file changed, 26 insertions(+), 64 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 6f5bbdce8fb4..8edeb4d823f0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -4082,67 +4082,29 @@ static const unsigned int vin4_clk_mux[] = {
 };
 
 /* - VIN5 ------------------------------------------------------------------- */
-static const unsigned int vin5_data8_pins[] = {
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin5_data8_mux[] = {
-	VI5_DATA0_MARK, VI5_DATA1_MARK,
-	VI5_DATA2_MARK, VI5_DATA3_MARK,
-	VI5_DATA4_MARK, VI5_DATA5_MARK,
-	VI5_DATA6_MARK, VI5_DATA7_MARK,
-};
-static const unsigned int vin5_data10_pins[] = {
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int vin5_data10_mux[] = {
-	VI5_DATA0_MARK, VI5_DATA1_MARK,
-	VI5_DATA2_MARK, VI5_DATA3_MARK,
-	VI5_DATA4_MARK, VI5_DATA5_MARK,
-	VI5_DATA6_MARK, VI5_DATA7_MARK,
-	VI5_DATA8_MARK,  VI5_DATA9_MARK,
-};
-static const unsigned int vin5_data12_pins[] = {
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-};
-static const unsigned int vin5_data12_mux[] = {
-	VI5_DATA0_MARK, VI5_DATA1_MARK,
-	VI5_DATA2_MARK, VI5_DATA3_MARK,
-	VI5_DATA4_MARK, VI5_DATA5_MARK,
-	VI5_DATA6_MARK, VI5_DATA7_MARK,
-	VI5_DATA8_MARK,  VI5_DATA9_MARK,
-	VI5_DATA10_MARK, VI5_DATA11_MARK,
-};
-static const unsigned int vin5_data16_pins[] = {
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+static const union vin_data16 vin5_data_pins = {
+	.data16 = {
+		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	},
 };
-static const unsigned int vin5_data16_mux[] = {
-	VI5_DATA0_MARK, VI5_DATA1_MARK,
-	VI5_DATA2_MARK, VI5_DATA3_MARK,
-	VI5_DATA4_MARK, VI5_DATA5_MARK,
-	VI5_DATA6_MARK, VI5_DATA7_MARK,
-	VI5_DATA8_MARK,  VI5_DATA9_MARK,
-	VI5_DATA10_MARK, VI5_DATA11_MARK,
-	VI5_DATA12_MARK, VI5_DATA13_MARK,
-	VI5_DATA14_MARK, VI5_DATA15_MARK,
+static const union vin_data16 vin5_data_mux = {
+	.data16 = {
+		VI5_DATA0_MARK, VI5_DATA1_MARK,
+		VI5_DATA2_MARK, VI5_DATA3_MARK,
+		VI5_DATA4_MARK, VI5_DATA5_MARK,
+		VI5_DATA6_MARK, VI5_DATA7_MARK,
+		VI5_DATA8_MARK,  VI5_DATA9_MARK,
+		VI5_DATA10_MARK, VI5_DATA11_MARK,
+		VI5_DATA12_MARK, VI5_DATA13_MARK,
+		VI5_DATA14_MARK, VI5_DATA15_MARK,
+	},
 };
 static const unsigned int vin5_sync_pins[] = {
 	/* HSYNC#, VSYNC# */
@@ -4512,10 +4474,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(vin4_field),
 	SH_PFC_PIN_GROUP(vin4_clkenb),
 	SH_PFC_PIN_GROUP(vin4_clk),
-	SH_PFC_PIN_GROUP(vin5_data8),
-	SH_PFC_PIN_GROUP(vin5_data10),
-	SH_PFC_PIN_GROUP(vin5_data12),
-	SH_PFC_PIN_GROUP(vin5_data16),
+	VIN_DATA_PIN_GROUP(vin5_data, 8),
+	VIN_DATA_PIN_GROUP(vin5_data, 10),
+	VIN_DATA_PIN_GROUP(vin5_data, 12),
+	VIN_DATA_PIN_GROUP(vin5_data, 16),
 	SH_PFC_PIN_GROUP(vin5_sync),
 	SH_PFC_PIN_GROUP(vin5_field),
 	SH_PFC_PIN_GROUP(vin5_clkenb),
-- 
2.17.1


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  parent reply	other threads:[~2020-08-21 10:58 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21  9:42 [cip-dev] [PATCH 00/36] Add Hihope RZ/G2H basic board support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 01/36] dt-bindings: power: Add r8a774e1 SYSC power domain definitions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 02/36] dt-bindings: power: renesas,rcar-sysc: Document r8a774e1 SYSC binding Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 03/36] soc: renesas: rcar-sysc: Add r8a774e1 support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 04/36] soc: renesas: Add Renesas R8A774E1 config option Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 05/36] dt-bindings: arm: renesas: Document RZ/G2H SoC DT bindings Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 06/36] soc: renesas: Identify RZ/G2H Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 07/36] dt-bindings: reset: rcar-rst: Document r8a774e1 reset module Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 08/36] soc: renesas: rcar-rst: Add support for RZ/G2H Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 09/36] clk: renesas: rcar-gen3: Add RPC clocks Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 10/36] clk: renesas: Add r8a774e1 CPG Core Clock Definitions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 11/36] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 12/36] clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 13/36] clk: renesas: rzg2: Mark RWDT clocks as critical Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 14/36] dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 15/36] clk: renesas: cpg-mssr: Add r8a774e1 support Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 16/36] arm64: defconfig: Enable R8A774E1 SoC Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 17/36] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 18/36] pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 19/36] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 20/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:42 ` Biju Das [this message]
2020-08-21  9:42 ` [cip-dev] [PATCH 22/36] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume Biju Das
2020-08-21  9:42 ` [cip-dev] [PATCH 23/36] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 24/36] pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 25/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 26/36] pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 27/36] pinctrl: sh-pfc: r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 28/36] pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3 Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 29/36] pinctrl: sh-pfc: pfc-r8a7795: " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 30/36] pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 31/36] dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC support Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 32/36] pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 " Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 33/36] arm64: dts: renesas: Initial r8a774e1 SoC device tree Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 34/36] dt-bindings: arm: renesas: Add HopeRun RZ/G2H boards Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 35/36] arm64: dts: renesas: Add HiHope RZ/G2H main board support Biju Das
2020-08-21  9:43 ` [cip-dev] [PATCH 36/36] arm64: dts: renesas: Add HiHope RZ/G2H sub " Biju Das
2020-08-23 19:03 ` [cip-dev] [PATCH 00/36] Add Hihope RZ/G2H basic " Pavel Machek
2020-08-23 23:04 ` Nobuhiro Iwamatsu

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