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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz
Date: Fri, 28 Aug 2020 10:24:07 +0100	[thread overview]
Message-ID: <20200828092413.22206-30-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200828092413.22206-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 53 +++++++++++++-------------------------
 1 file changed, 18 insertions(+), 35 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6d10e2ac2c7..0d5bcf6c1ed 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -142,6 +142,17 @@ static int pred_gvec_reg_size(DisasContext *s)
     return size_for_gvec(pred_full_reg_size(s));
 }
 
+/* Invoke an out-of-line helper on 3 Zregs. */
+static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
+                             int rd, int rn, int rm, int data)
+{
+    unsigned vsz = vec_full_reg_size(s);
+    tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
+                       vec_full_reg_offset(s, rn),
+                       vec_full_reg_offset(s, rm),
+                       vsz, vsz, data, fn);
+}
+
 /* Invoke an out-of-line helper on 2 Zregs and a predicate. */
 static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
                              int rd, int rn, int pg, int data)
@@ -769,11 +780,7 @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
         return false;
     }
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, 0, fn);
+        gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
     }
     return true;
 }
@@ -947,11 +954,7 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
 static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
 {
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, a->imm, fn);
+        gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
     }
     return true;
 }
@@ -1012,11 +1015,7 @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
         return false;
     }
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, 0, fns[a->esz]);
+        gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
     }
     return true;
 }
@@ -2067,11 +2066,7 @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
     };
 
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, 0, fns[a->esz]);
+        gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
     }
     return true;
 }
@@ -2244,11 +2239,7 @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
                             gen_helper_gvec_3 *fn)
 {
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, data, fn);
+        gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
     }
     return true;
 }
@@ -3373,11 +3364,7 @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
     };
 
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, 0, fns[a->u][a->sz]);
+        gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
     }
     return true;
 }
@@ -3390,11 +3377,7 @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
     };
 
     if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
-                           vec_full_reg_offset(s, a->rn),
-                           vec_full_reg_offset(s, a->rm),
-                           vsz, vsz, a->index, fns[a->u][a->sz]);
+        gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
     }
     return true;
 }
-- 
2.20.1



  parent reply	other threads:[~2020-08-28  9:39 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-28  9:23 [PULL 00/35] target-arm queue Peter Maydell
2020-08-28  9:23 ` [PULL 01/35] hw/arm/sbsa-ref: fix typo breaking PCIe IRQs Peter Maydell
2020-08-28  9:23 ` [PULL 02/35] hw/clock: Remove unused clock_init*() functions Peter Maydell
2020-08-28  9:23 ` [PULL 03/35] hw/clock: Let clock_set() return boolean value Peter Maydell
2020-08-28  9:23 ` [PULL 04/35] hw/clock: Only propagate clock changes if the clock is changed Peter Maydell
2020-08-28  9:23 ` [PULL 05/35] hw/arm/musicpal: Use AddressSpace for DMA transfers Peter Maydell
2020-08-28  9:23 ` [PULL 06/35] target/arm: Clarify HCR_EL2 ARMCPRegInfo type Peter Maydell
2020-08-28  9:23 ` [PULL 07/35] target/arm: Pass the entire mte descriptor to mte_check_fail Peter Maydell
2020-08-28  9:23 ` [PULL 08/35] target/arm: Fill in the WnR syndrome bit in mte_check_fail Peter Maydell
2020-08-28  9:23 ` [PULL 09/35] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers Peter Maydell
2020-08-28  9:23 ` [PULL 10/35] hw/net/allwinner-sun8i-emac: " Peter Maydell
2020-08-28  9:23 ` [PULL 11/35] hw/arm/xilinx_zynq: Uninline cadence_uart_create() Peter Maydell
2020-08-28  9:23 ` [PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize Peter Maydell
2020-08-28  9:23 ` [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in() Peter Maydell
2020-08-28  9:23 ` [PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize Peter Maydell
2020-08-28  9:23 ` [PULL 15/35] hw/misc/unimp: Display value after offset Peter Maydell
2020-08-28  9:23 ` [PULL 16/35] hw/misc/unimp: Display the value with width of the access size Peter Maydell
2020-08-28  9:23 ` [PULL 17/35] hw/misc/unimp: Display the offset with width of the region size Peter Maydell
2020-08-28  9:23 ` [PULL 18/35] armsse: Define ARMSSEClass correctly Peter Maydell
2020-08-28  9:23 ` [PULL 19/35] qemu/int128: Add int128_lshift Peter Maydell
2020-08-28  9:23 ` [PULL 20/35] target/arm: Split out gen_gvec_fn_zz Peter Maydell
2020-08-28  9:23 ` [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn Peter Maydell
2020-08-28  9:24 ` [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert Peter Maydell
2020-08-28  9:24 ` [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p Peter Maydell
2020-08-28  9:24 ` [PULL 24/35] target/arm: Clean up 4-operand predicate expansion Peter Maydell
2020-08-28  9:24 ` [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp Peter Maydell
2020-08-28  9:24 ` [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp Peter Maydell
2020-08-28  9:24 ` [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_* Peter Maydell
2020-08-28  9:24 ` [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp Peter Maydell
2020-08-28  9:24 ` Peter Maydell [this message]
2020-08-28  9:24 ` [PULL 30/35] target/arm: Split out gen_gvec_ool_zz Peter Maydell
2020-08-28  9:24 ` [PULL 31/35] target/arm: Tidy SVE tszimm shift formats Peter Maydell
2020-08-28  9:24 ` [PULL 32/35] target/arm: Generalize inl_qrdmlah_* helper functions Peter Maydell
2020-08-28  9:24 ` [PULL 33/35] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd Peter Maydell
2020-08-28  9:24 ` [PULL 34/35] target/arm: Convert integer multiply-add " Peter Maydell
2020-08-28  9:24 ` [PULL 35/35] target/arm: Convert sq{, r}dmulh " Peter Maydell
2020-08-28 17:37 ` [PULL 00/35] target-arm queue Peter Maydell

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