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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: [PATCH v3 3/8] x86/msr: explicitly handle AMD DE_CFG
Date: Tue, 1 Sep 2020 12:54:40 +0200	[thread overview]
Message-ID: <20200901105445.22277-4-roger.pau@citrix.com> (raw)
In-Reply-To: <20200901105445.22277-1-roger.pau@citrix.com>

Report LFENCE_SERIALISE unconditionally for DE_CFG on AMD hardware and
silently drop writes.

Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Changes since v2:
 - Drop the bot_cpu checks and don't attempt to read the MSR, just
   return LFENCE_SERIALISE unconditionally.
 - Add a comment about OpenBSD panicking if writing to the MSR
   triggers a #GP.

Changes since v1:
 - New in this version.
---
 xen/arch/x86/msr.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index a478b91f23..e84107ac7b 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -292,6 +292,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
         *val = msrs->tsc_aux;
         break;
 
+    case MSR_AMD64_DE_CFG:
+        if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+            goto gp_fault;
+        *val = AMD64_DE_CFG_LFENCE_SERIALISE;
+        break;
+
     case MSR_AMD64_DR0_ADDRESS_MASK:
     case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK:
         if ( !cp->extd.dbext )
@@ -517,6 +523,15 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
             wrmsr_tsc_aux(val);
         break;
 
+    case MSR_AMD64_DE_CFG:
+        /*
+         * OpenBSD 6.7 will panic if writing to DE_CFG triggers a #GP:
+         * https://www.illumos.org/issues/12998
+         */
+        if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+            goto gp_fault;
+        break;
+
     case MSR_AMD64_DR0_ADDRESS_MASK:
     case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK:
         if ( !cp->extd.dbext || val != (uint32_t)val )
-- 
2.28.0



  parent reply	other threads:[~2020-09-01 11:10 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-01 10:54 [PATCH v3 0/8] x86: switch default MSR behavior Roger Pau Monne
2020-09-01 10:54 ` [PATCH v3 1/8] x86/vmx: handle writes to MISC_ENABLE MSR Roger Pau Monne
2020-09-04  8:34   ` Jan Beulich
2020-09-07  3:25   ` Tian, Kevin
2020-09-07  7:22     ` Jan Beulich
2020-09-01 10:54 ` [PATCH v3 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs Roger Pau Monne
2020-09-04  8:36   ` Jan Beulich
2020-09-04  9:47     ` Andrew Cooper
2020-09-01 10:54 ` Roger Pau Monne [this message]
2020-09-02 20:49   ` [PATCH v3 3/8] x86/msr: explicitly handle AMD DE_CFG Andrew Cooper
2020-09-01 10:54 ` [PATCH v3 4/8] x86/svm: handle BU_CFG and BU_CFG2 with cases Roger Pau Monne
2020-09-02 21:02   ` Andrew Cooper
2020-09-03  8:15     ` Roger Pau Monné
2020-09-04  8:39       ` Jan Beulich
2020-09-03  8:29     ` Jan Beulich
2020-09-01 10:54 ` [PATCH v3 5/8] x86/pv: allow reading FEATURE_CONTROL MSR Roger Pau Monne
2020-09-02 20:56   ` Andrew Cooper
2020-09-03 13:33     ` Roger Pau Monné
2020-09-03 14:06       ` Andrew Cooper
2020-09-03 14:10         ` Roger Pau Monné
2020-09-01 10:54 ` [PATCH v3 6/8] x86/pv: disallow access to unknown MSRs Roger Pau Monne
2020-09-01 10:54 ` [PATCH v3 7/8] x86/hvm: Disallow " Roger Pau Monne
2020-09-04  8:53   ` Jan Beulich
2020-09-04  9:44     ` Andrew Cooper
2020-09-04  9:58       ` Jan Beulich
2020-09-04 11:13     ` Roger Pau Monné
2020-09-07  3:31   ` Tian, Kevin
2020-09-01 10:54 ` [PATCH v3 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Roger Pau Monne

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