From: Paul Cercueil <paul@crapouillou.net>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: od@zcrc.me, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH 5/5] clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Date: Thu, 3 Sep 2020 03:50:48 +0200 [thread overview]
Message-ID: <20200903015048.3091523-5-paul@crapouillou.net> (raw)
In-Reply-To: <20200903015048.3091523-1-paul@crapouillou.net>
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/clk/ingenic/cgu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index a1a4f1adaa3a..dac6edc670cc 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -445,6 +445,8 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
else if (clk_info->type & CGU_CLK_FIXDIV)
div = clk_info->fixdiv.div;
+ else if (clk_hw_can_set_rate_parent(hw))
+ *parent_rate = req_rate;
return DIV_ROUND_UP(*parent_rate, div);
}
--
2.28.0
next prev parent reply other threads:[~2020-09-03 1:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 1:50 [PATCH 1/5] clk: ingenic: Use to_clk_info() macro for all clocks Paul Cercueil
2020-09-03 1:50 ` [PATCH 2/5] clk: ingenic: Use readl_poll_timeout instead of custom loop Paul Cercueil
2020-10-14 3:06 ` Stephen Boyd
2020-09-03 1:50 ` [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL Paul Cercueil
2020-10-14 3:06 ` Stephen Boyd
2020-09-03 1:50 ` [PATCH 4/5] clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT Paul Cercueil
2020-10-14 3:06 ` Stephen Boyd
2020-09-03 1:50 ` Paul Cercueil [this message]
2020-10-14 3:06 ` [PATCH 5/5] clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate Stephen Boyd
2020-10-14 3:06 ` [PATCH 1/5] clk: ingenic: Use to_clk_info() macro for all clocks Stephen Boyd
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