From: Michael Tretter <m.tretter@pengutronix.de> To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: kernel@pengutronix.de, Laurent.pinchart@ideasonboard.com, krzk@kernel.org, narmstrong@baylibre.com, Michael Tretter <m.tretter@pengutronix.de> Subject: [PATCH 11/16] drm/exynos: shift register values to fields on write Date: Thu, 3 Sep 2020 18:57:12 +0200 [thread overview] Message-ID: <20200903165717.1272492-12-m.tretter@pengutronix.de> (raw) In-Reply-To: <20200903165717.1272492-1-m.tretter@pengutronix.de> The phy timings are already shifted to the field position. If the driver is reused on multiple platforms, this exposes the field positions to the platform code. Store only the timing values in the platform data and shift the value to the field when writing the fields to the registers. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 88 +++++++++++++------------ 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 3bf4ae0fe6cc..21db18ae0772 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -397,54 +397,54 @@ static const unsigned int reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), + [PHYCTRL_ULPS_EXIT] = 0x0af, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), + [PHYTIMING_LPX] = 0x06, + [PHYTIMING_HS_EXIT] = 0x0b, + [PHYTIMING_CLK_PREPARE] = 0x07, + [PHYTIMING_CLK_ZERO] = 0x27, + [PHYTIMING_CLK_POST] = 0x0d, + [PHYTIMING_CLK_TRAIL] = 0x08, + [PHYTIMING_HS_PREPARE] = 0x09, + [PHYTIMING_HS_ZERO] = 0x0d, + [PHYTIMING_HS_TRAIL] = 0x0b, }; static const unsigned int exynos5422_reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), + [PHYCTRL_ULPS_EXIT] = 0xaf, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), + [PHYTIMING_LPX] = 0x08, + [PHYTIMING_HS_EXIT] = 0x0d, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x30, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x0a, + [PHYTIMING_HS_PREPARE] = 0x0c, + [PHYTIMING_HS_ZERO] = 0x11, + [PHYTIMING_HS_TRAIL] = 0x0d, }; static const unsigned int exynos5433_reg_values[] = { [RESET_TYPE] = DSIM_FUNCRST, [PLL_TIMER] = 22200, [STOP_STATE_CNT] = 0xa, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), - [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, - [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), + [PHYCTRL_ULPS_EXIT] = 0x190, + [PHYCTRL_VREG_LP] = 1, + [PHYCTRL_SLEW_UP] = 1, + [PHYTIMING_LPX] = 0x07, + [PHYTIMING_HS_EXIT] = 0x0c, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x2d, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x09, + [PHYTIMING_HS_PREPARE] = 0x0b, + [PHYTIMING_HS_ZERO] = 0x10, + [PHYTIMING_HS_TRAIL] = 0x0c, }; static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { @@ -696,8 +696,11 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) return; /* B D-PHY: D-PHY Master & Slave Analog Block control */ - reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | - reg_values[PHYCTRL_SLEW_UP]; + reg = DSIM_PHYCTRL_ULPS_EXIT(reg_values[PHYCTRL_ULPS_EXIT]); + if (reg_values[PHYCTRL_VREG_LP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_VREG_LP; + if (reg_values[PHYCTRL_SLEW_UP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP; exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); /* @@ -705,7 +708,8 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + reg = DSIM_PHYTIMING_LPX(reg_values[PHYTIMING_LPX]) | + DSIM_PHYTIMING_HS_EXIT(reg_values[PHYTIMING_HS_EXIT]); exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); /* @@ -721,11 +725,10 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; - + reg = DSIM_PHYTIMING1_CLK_PREPARE(reg_values[PHYTIMING_CLK_PREPARE]) | + DSIM_PHYTIMING1_CLK_ZERO(reg_values[PHYTIMING_CLK_ZERO]) | + DSIM_PHYTIMING1_CLK_POST(reg_values[PHYTIMING_CLK_POST]) | + DSIM_PHYTIMING1_CLK_TRAIL(reg_values[PHYTIMING_CLK_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); /* @@ -737,8 +740,9 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + reg = DSIM_PHYTIMING2_HS_PREPARE(reg_values[PHYTIMING_HS_PREPARE]) | + DSIM_PHYTIMING2_HS_ZERO(reg_values[PHYTIMING_HS_ZERO]) | + DSIM_PHYTIMING2_HS_TRAIL(reg_values[PHYTIMING_HS_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); } -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Michael Tretter <m.tretter@pengutronix.de>, krzk@kernel.org, Laurent.pinchart@ideasonboard.com, kernel@pengutronix.de, narmstrong@baylibre.com Subject: [PATCH 11/16] drm/exynos: shift register values to fields on write Date: Thu, 3 Sep 2020 18:57:12 +0200 [thread overview] Message-ID: <20200903165717.1272492-12-m.tretter@pengutronix.de> (raw) In-Reply-To: <20200903165717.1272492-1-m.tretter@pengutronix.de> The phy timings are already shifted to the field position. If the driver is reused on multiple platforms, this exposes the field positions to the platform code. Store only the timing values in the platform data and shift the value to the field when writing the fields to the registers. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 88 +++++++++++++------------ 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 3bf4ae0fe6cc..21db18ae0772 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -397,54 +397,54 @@ static const unsigned int reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), + [PHYCTRL_ULPS_EXIT] = 0x0af, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), + [PHYTIMING_LPX] = 0x06, + [PHYTIMING_HS_EXIT] = 0x0b, + [PHYTIMING_CLK_PREPARE] = 0x07, + [PHYTIMING_CLK_ZERO] = 0x27, + [PHYTIMING_CLK_POST] = 0x0d, + [PHYTIMING_CLK_TRAIL] = 0x08, + [PHYTIMING_HS_PREPARE] = 0x09, + [PHYTIMING_HS_ZERO] = 0x0d, + [PHYTIMING_HS_TRAIL] = 0x0b, }; static const unsigned int exynos5422_reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), + [PHYCTRL_ULPS_EXIT] = 0xaf, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), + [PHYTIMING_LPX] = 0x08, + [PHYTIMING_HS_EXIT] = 0x0d, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x30, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x0a, + [PHYTIMING_HS_PREPARE] = 0x0c, + [PHYTIMING_HS_ZERO] = 0x11, + [PHYTIMING_HS_TRAIL] = 0x0d, }; static const unsigned int exynos5433_reg_values[] = { [RESET_TYPE] = DSIM_FUNCRST, [PLL_TIMER] = 22200, [STOP_STATE_CNT] = 0xa, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), - [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, - [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), + [PHYCTRL_ULPS_EXIT] = 0x190, + [PHYCTRL_VREG_LP] = 1, + [PHYCTRL_SLEW_UP] = 1, + [PHYTIMING_LPX] = 0x07, + [PHYTIMING_HS_EXIT] = 0x0c, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x2d, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x09, + [PHYTIMING_HS_PREPARE] = 0x0b, + [PHYTIMING_HS_ZERO] = 0x10, + [PHYTIMING_HS_TRAIL] = 0x0c, }; static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { @@ -696,8 +696,11 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) return; /* B D-PHY: D-PHY Master & Slave Analog Block control */ - reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | - reg_values[PHYCTRL_SLEW_UP]; + reg = DSIM_PHYCTRL_ULPS_EXIT(reg_values[PHYCTRL_ULPS_EXIT]); + if (reg_values[PHYCTRL_VREG_LP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_VREG_LP; + if (reg_values[PHYCTRL_SLEW_UP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP; exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); /* @@ -705,7 +708,8 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + reg = DSIM_PHYTIMING_LPX(reg_values[PHYTIMING_LPX]) | + DSIM_PHYTIMING_HS_EXIT(reg_values[PHYTIMING_HS_EXIT]); exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); /* @@ -721,11 +725,10 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; - + reg = DSIM_PHYTIMING1_CLK_PREPARE(reg_values[PHYTIMING_CLK_PREPARE]) | + DSIM_PHYTIMING1_CLK_ZERO(reg_values[PHYTIMING_CLK_ZERO]) | + DSIM_PHYTIMING1_CLK_POST(reg_values[PHYTIMING_CLK_POST]) | + DSIM_PHYTIMING1_CLK_TRAIL(reg_values[PHYTIMING_CLK_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); /* @@ -737,8 +740,9 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + reg = DSIM_PHYTIMING2_HS_PREPARE(reg_values[PHYTIMING_HS_PREPARE]) | + DSIM_PHYTIMING2_HS_ZERO(reg_values[PHYTIMING_HS_ZERO]) | + DSIM_PHYTIMING2_HS_TRAIL(reg_values[PHYTIMING_HS_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); } -- 2.20.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-03 16:57 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-03 16:57 [PATCH 00/16] drm/exynos: Convert driver to drm bridge Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 01/16] drm/encoder: remove obsolete documentation of bridge Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 22:04 ` Laurent Pinchart 2020-09-03 22:04 ` Laurent Pinchart 2020-09-03 16:57 ` [PATCH 02/16] drm/exynos: extract helper functions for probe Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-04 9:04 ` Marek Szyprowski 2020-09-04 9:04 ` Marek Szyprowski 2020-09-04 9:21 ` Marek Szyprowski 2020-09-04 9:21 ` Marek Szyprowski 2020-09-03 16:57 ` [PATCH 03/16] drm/exynos: remove in_bridge_node from exynos_dsi Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 04/16] drm/exynos: implement a drm bridge Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 05/16] drm/exynos: convert encoder functions to bridge function Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 06/16] drm/exynos: configure mode on drm bridge Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 07/16] drm/exynos: get encoder from bridge whenever possible Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 08/16] drm/exynos: use exynos_dsi as drvdata Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 09/16] drm/exynos: call probe helper from bind Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 10/16] drm/exynos: move dsi host registration to probe helper Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` Michael Tretter [this message] 2020-09-03 16:57 ` [PATCH 11/16] drm/exynos: shift register values to fields on write Michael Tretter 2020-09-03 16:57 ` [PATCH 12/16] drm/exynos: use identifier instead of register offsets Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 13/16] drm/exynos: add callback for tearing effect handler Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 14/16] drm/exynos: add callback for enabling i80 mode Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 15/16] drm/exynos: split out platform specific code Michael Tretter 2020-09-03 16:57 ` Michael Tretter 2020-09-03 16:57 ` [PATCH 16/16] drm/exynos: move bridge driver to bridges Michael Tretter 2020-09-03 20:08 ` [PATCH 00/16] drm/exynos: Convert driver to drm bridge Krzysztof Kozlowski 2020-09-03 20:08 ` Krzysztof Kozlowski 2020-09-04 8:31 ` Marek Szyprowski 2020-09-04 8:31 ` Marek Szyprowski 2020-09-04 12:20 ` Michael Tretter 2020-09-04 12:20 ` Michael Tretter
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