From: Michael Tretter <m.tretter@pengutronix.de> To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: kernel@pengutronix.de, Laurent.pinchart@ideasonboard.com, krzk@kernel.org, narmstrong@baylibre.com, b.zolnierkie@samsung.com, sylvester.nawrocki@gmail.com, a.hajda@samsung.com, inki.dae@samsung.com, jy0922.shim@samsung.com, sw0312.kim@samsung.com, Michael Tretter <m.tretter@pengutronix.de> Subject: [PATCH v2 06/16] drm/exynos: shift register values to fields on write Date: Fri, 11 Sep 2020 15:54:03 +0200 [thread overview] Message-ID: <20200911135413.3654800-7-m.tretter@pengutronix.de> (raw) In-Reply-To: <20200911135413.3654800-1-m.tretter@pengutronix.de> The phy timings are already shifted to the field position. If the driver is reused on multiple platforms, this exposes the field positions to the platform code. Store only the timing values in the platform data and shift the value to the field when writing the fields to the registers. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- v2: none --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 88 +++++++++++++------------ 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 41000214a5fe..0f2cac7ed944 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -399,54 +399,54 @@ static const unsigned int reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), + [PHYCTRL_ULPS_EXIT] = 0x0af, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), + [PHYTIMING_LPX] = 0x06, + [PHYTIMING_HS_EXIT] = 0x0b, + [PHYTIMING_CLK_PREPARE] = 0x07, + [PHYTIMING_CLK_ZERO] = 0x27, + [PHYTIMING_CLK_POST] = 0x0d, + [PHYTIMING_CLK_TRAIL] = 0x08, + [PHYTIMING_HS_PREPARE] = 0x09, + [PHYTIMING_HS_ZERO] = 0x0d, + [PHYTIMING_HS_TRAIL] = 0x0b, }; static const unsigned int exynos5422_reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), + [PHYCTRL_ULPS_EXIT] = 0xaf, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), + [PHYTIMING_LPX] = 0x08, + [PHYTIMING_HS_EXIT] = 0x0d, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x30, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x0a, + [PHYTIMING_HS_PREPARE] = 0x0c, + [PHYTIMING_HS_ZERO] = 0x11, + [PHYTIMING_HS_TRAIL] = 0x0d, }; static const unsigned int exynos5433_reg_values[] = { [RESET_TYPE] = DSIM_FUNCRST, [PLL_TIMER] = 22200, [STOP_STATE_CNT] = 0xa, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), - [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, - [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), + [PHYCTRL_ULPS_EXIT] = 0x190, + [PHYCTRL_VREG_LP] = 1, + [PHYCTRL_SLEW_UP] = 1, + [PHYTIMING_LPX] = 0x07, + [PHYTIMING_HS_EXIT] = 0x0c, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x2d, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x09, + [PHYTIMING_HS_PREPARE] = 0x0b, + [PHYTIMING_HS_ZERO] = 0x10, + [PHYTIMING_HS_TRAIL] = 0x0c, }; static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { @@ -698,8 +698,11 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) return; /* B D-PHY: D-PHY Master & Slave Analog Block control */ - reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | - reg_values[PHYCTRL_SLEW_UP]; + reg = DSIM_PHYCTRL_ULPS_EXIT(reg_values[PHYCTRL_ULPS_EXIT]); + if (reg_values[PHYCTRL_VREG_LP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_VREG_LP; + if (reg_values[PHYCTRL_SLEW_UP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP; exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); /* @@ -707,7 +710,8 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + reg = DSIM_PHYTIMING_LPX(reg_values[PHYTIMING_LPX]) | + DSIM_PHYTIMING_HS_EXIT(reg_values[PHYTIMING_HS_EXIT]); exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); /* @@ -723,11 +727,10 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; - + reg = DSIM_PHYTIMING1_CLK_PREPARE(reg_values[PHYTIMING_CLK_PREPARE]) | + DSIM_PHYTIMING1_CLK_ZERO(reg_values[PHYTIMING_CLK_ZERO]) | + DSIM_PHYTIMING1_CLK_POST(reg_values[PHYTIMING_CLK_POST]) | + DSIM_PHYTIMING1_CLK_TRAIL(reg_values[PHYTIMING_CLK_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); /* @@ -739,8 +742,9 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + reg = DSIM_PHYTIMING2_HS_PREPARE(reg_values[PHYTIMING_HS_PREPARE]) | + DSIM_PHYTIMING2_HS_ZERO(reg_values[PHYTIMING_HS_ZERO]) | + DSIM_PHYTIMING2_HS_TRAIL(reg_values[PHYTIMING_HS_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); } -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: jy0922.shim@samsung.com, b.zolnierkie@samsung.com, narmstrong@baylibre.com, sw0312.kim@samsung.com, Michael Tretter <m.tretter@pengutronix.de>, krzk@kernel.org, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, kernel@pengutronix.de, sylvester.nawrocki@gmail.com Subject: [PATCH v2 06/16] drm/exynos: shift register values to fields on write Date: Fri, 11 Sep 2020 15:54:03 +0200 [thread overview] Message-ID: <20200911135413.3654800-7-m.tretter@pengutronix.de> (raw) In-Reply-To: <20200911135413.3654800-1-m.tretter@pengutronix.de> The phy timings are already shifted to the field position. If the driver is reused on multiple platforms, this exposes the field positions to the platform code. Store only the timing values in the platform data and shift the value to the field when writing the fields to the registers. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- v2: none --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 88 +++++++++++++------------ 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 41000214a5fe..0f2cac7ed944 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -399,54 +399,54 @@ static const unsigned int reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), + [PHYCTRL_ULPS_EXIT] = 0x0af, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), + [PHYTIMING_LPX] = 0x06, + [PHYTIMING_HS_EXIT] = 0x0b, + [PHYTIMING_CLK_PREPARE] = 0x07, + [PHYTIMING_CLK_ZERO] = 0x27, + [PHYTIMING_CLK_POST] = 0x0d, + [PHYTIMING_CLK_TRAIL] = 0x08, + [PHYTIMING_HS_PREPARE] = 0x09, + [PHYTIMING_HS_ZERO] = 0x0d, + [PHYTIMING_HS_TRAIL] = 0x0b, }; static const unsigned int exynos5422_reg_values[] = { [RESET_TYPE] = DSIM_SWRST, [PLL_TIMER] = 500, [STOP_STATE_CNT] = 0xf, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), + [PHYCTRL_ULPS_EXIT] = 0xaf, [PHYCTRL_VREG_LP] = 0, [PHYCTRL_SLEW_UP] = 0, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), + [PHYTIMING_LPX] = 0x08, + [PHYTIMING_HS_EXIT] = 0x0d, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x30, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x0a, + [PHYTIMING_HS_PREPARE] = 0x0c, + [PHYTIMING_HS_ZERO] = 0x11, + [PHYTIMING_HS_TRAIL] = 0x0d, }; static const unsigned int exynos5433_reg_values[] = { [RESET_TYPE] = DSIM_FUNCRST, [PLL_TIMER] = 22200, [STOP_STATE_CNT] = 0xa, - [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), - [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, - [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, - [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), - [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), - [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), - [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), - [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), - [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), - [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), - [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), - [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), + [PHYCTRL_ULPS_EXIT] = 0x190, + [PHYCTRL_VREG_LP] = 1, + [PHYCTRL_SLEW_UP] = 1, + [PHYTIMING_LPX] = 0x07, + [PHYTIMING_HS_EXIT] = 0x0c, + [PHYTIMING_CLK_PREPARE] = 0x09, + [PHYTIMING_CLK_ZERO] = 0x2d, + [PHYTIMING_CLK_POST] = 0x0e, + [PHYTIMING_CLK_TRAIL] = 0x09, + [PHYTIMING_HS_PREPARE] = 0x0b, + [PHYTIMING_HS_ZERO] = 0x10, + [PHYTIMING_HS_TRAIL] = 0x0c, }; static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { @@ -698,8 +698,11 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) return; /* B D-PHY: D-PHY Master & Slave Analog Block control */ - reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | - reg_values[PHYCTRL_SLEW_UP]; + reg = DSIM_PHYCTRL_ULPS_EXIT(reg_values[PHYCTRL_ULPS_EXIT]); + if (reg_values[PHYCTRL_VREG_LP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_VREG_LP; + if (reg_values[PHYCTRL_SLEW_UP]) + reg |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP; exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); /* @@ -707,7 +710,8 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + reg = DSIM_PHYTIMING_LPX(reg_values[PHYTIMING_LPX]) | + DSIM_PHYTIMING_HS_EXIT(reg_values[PHYTIMING_HS_EXIT]); exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); /* @@ -723,11 +727,10 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; - + reg = DSIM_PHYTIMING1_CLK_PREPARE(reg_values[PHYTIMING_CLK_PREPARE]) | + DSIM_PHYTIMING1_CLK_ZERO(reg_values[PHYTIMING_CLK_ZERO]) | + DSIM_PHYTIMING1_CLK_POST(reg_values[PHYTIMING_CLK_POST]) | + DSIM_PHYTIMING1_CLK_TRAIL(reg_values[PHYTIMING_CLK_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); /* @@ -739,8 +742,9 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + reg = DSIM_PHYTIMING2_HS_PREPARE(reg_values[PHYTIMING_HS_PREPARE]) | + DSIM_PHYTIMING2_HS_ZERO(reg_values[PHYTIMING_HS_ZERO]) | + DSIM_PHYTIMING2_HS_TRAIL(reg_values[PHYTIMING_HS_TRAIL]); exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); } -- 2.20.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-11 16:53 UTC|newest] Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20200911165401epcas1p3c7ee84dd01db93f472d6fa21c1100f29@epcas1p3.samsung.com> 2020-09-11 13:53 ` [PATCH v2 00/16] drm/exynos: Convert driver to drm bridge Michael Tretter 2020-09-11 13:53 ` Michael Tretter 2020-09-11 13:53 ` [PATCH v2 01/16] drm/encoder: remove obsolete documentation of bridge Michael Tretter 2020-09-11 13:53 ` Michael Tretter 2020-11-07 15:07 ` Adam Ford 2020-11-07 15:07 ` Adam Ford 2020-11-10 8:46 ` Michael Tretter 2020-11-10 8:46 ` Michael Tretter 2020-11-07 22:17 ` Sam Ravnborg 2020-11-07 22:17 ` Sam Ravnborg 2020-09-11 13:53 ` [PATCH v2 02/16] drm/exynos: remove in_bridge_node from exynos_dsi Michael Tretter 2020-09-11 13:53 ` Michael Tretter 2020-11-07 22:19 ` Sam Ravnborg 2020-11-07 22:19 ` Sam Ravnborg 2020-11-09 2:24 ` Inki Dae 2020-09-11 13:54 ` [PATCH v2 03/16] drm/exynos: use exynos_dsi as drvdata Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-11-07 22:24 ` Sam Ravnborg 2020-11-07 22:24 ` Sam Ravnborg 2020-11-09 2:24 ` Inki Dae 2020-11-09 2:24 ` Inki Dae 2020-09-11 13:54 ` [PATCH v2 04/16] drm/exynos: extract helper functions for probe Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-11-07 22:27 ` Sam Ravnborg 2020-11-07 22:27 ` Sam Ravnborg 2020-11-09 2:52 ` Inki Dae 2020-11-09 2:52 ` Inki Dae 2020-09-11 13:54 ` [PATCH v2 05/16] drm/exynos: move dsi host registration to probe Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` Michael Tretter [this message] 2020-09-11 13:54 ` [PATCH v2 06/16] drm/exynos: shift register values to fields on write Michael Tretter 2020-11-07 22:39 ` Sam Ravnborg 2020-11-07 22:39 ` Sam Ravnborg 2020-11-10 8:28 ` Michael Tretter 2020-11-10 8:28 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 07/16] drm/exynos: use identifier instead of register offsets Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 08/16] drm/exynos: add host_ops callback for platform drivers Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-15 17:07 ` Andrzej Hajda 2020-09-15 17:07 ` Andrzej Hajda 2020-09-15 18:02 ` Michael Tretter 2020-09-15 18:02 ` Michael Tretter 2020-09-16 22:01 ` Andrzej Hajda 2020-09-16 22:01 ` Andrzej Hajda 2020-09-11 13:54 ` [PATCH v2 09/16] drm/exynos: add callback for tearing effect handler Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 10/16] drm/exynos: implement a drm bridge Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-14 8:29 ` Marek Szyprowski 2020-09-14 8:29 ` Marek Szyprowski 2020-09-14 12:31 ` Marek Szyprowski 2020-09-14 12:31 ` Marek Szyprowski 2020-09-14 20:01 ` Michael Tretter 2020-09-14 20:01 ` Michael Tretter 2020-09-14 21:19 ` Andrzej Hajda 2020-09-14 21:19 ` Andrzej Hajda 2020-09-15 19:40 ` Andrzej Hajda 2020-09-15 19:40 ` Andrzej Hajda 2021-02-01 16:33 ` Michael Tretter 2021-02-01 16:33 ` Michael Tretter 2021-02-03 20:31 ` Michael Tretter 2021-02-03 20:31 ` Michael Tretter 2021-02-04 10:17 ` Daniel Vetter 2021-02-04 10:17 ` Daniel Vetter 2021-02-04 10:56 ` Michael Tretter 2021-02-04 10:56 ` Michael Tretter 2021-02-04 16:05 ` Daniel Vetter 2021-02-04 16:05 ` Daniel Vetter 2021-02-04 16:28 ` Andrzej Hajda 2021-02-04 16:28 ` Andrzej Hajda 2021-02-04 17:19 ` Daniel Vetter 2021-02-04 17:19 ` Daniel Vetter 2021-02-04 17:26 ` Laurent Pinchart 2021-02-04 17:26 ` Laurent Pinchart 2021-02-04 17:46 ` Daniel Vetter 2021-02-04 17:46 ` Daniel Vetter 2021-02-10 9:10 ` Frieder Schrempf 2021-02-10 9:10 ` Frieder Schrempf 2021-02-18 8:04 ` Michael Tretter 2021-02-18 8:04 ` Michael Tretter 2021-02-18 16:02 ` Andrzej Hajda 2021-02-18 16:02 ` Andrzej Hajda 2021-02-23 12:07 ` Daniel Vetter 2021-02-23 12:07 ` Daniel Vetter 2021-04-20 11:42 ` Frieder Schrempf 2021-04-20 11:42 ` Frieder Schrempf 2021-04-20 14:27 ` Laurent Pinchart 2021-04-20 14:27 ` Laurent Pinchart 2020-09-11 13:54 ` [PATCH v2 11/16] drm/exynos: convert encoder functions to bridge function Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 12/16] drm/exynos: configure mode on drm bridge Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 13/16] drm/exynos: get encoder from bridge whenever possible Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 14/16] drm/exynos: add API functions for platform drivers Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 15/16] drm/exynos: split out platform specific code Michael Tretter 2020-09-11 13:54 ` Michael Tretter 2020-09-11 13:54 ` [PATCH v2 16/16] drm/exynos: move bridge driver to bridges Michael Tretter 2020-09-16 7:58 ` Daniel Vetter 2020-09-16 8:58 ` Michael Tretter 2020-09-16 9:03 ` Daniel Vetter 2020-11-09 3:15 ` [PATCH v2 00/16] drm/exynos: Convert driver to drm bridge Inki Dae 2020-11-09 3:15 ` Inki Dae 2020-11-10 8:13 ` Michael Tretter 2020-11-10 8:13 ` Michael Tretter 2020-11-10 12:34 ` Marek Szyprowski 2020-11-10 12:34 ` Marek Szyprowski 2020-11-10 18:52 ` Sam Ravnborg 2020-11-11 3:04 ` Inki Dae 2020-11-11 3:04 ` Inki Dae 2020-11-11 3:11 ` Inki Dae 2020-11-11 3:11 ` Inki Dae 2020-11-11 10:18 ` Michael Tretter 2020-11-11 10:18 ` Michael Tretter 2020-11-13 9:34 ` Inki Dae 2020-11-13 9:34 ` Inki Dae
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