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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
	Takashi Iwai <tiwai@suse.com>
Cc: alsa-devel@alsa-project.org, <linux-kernel@vger.kernel.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH 1/3] ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization
Date: Fri, 11 Sep 2020 19:31:38 +0200	[thread overview]
Message-ID: <20200911173140.29984-2-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20200911173140.29984-1-miquel.raynal@bootlin.com>

As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.

The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 sound/soc/codecs/tlv320aic32x4-clk.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c
index 156c153c12ab..2f78e6820c75 100644
--- a/sound/soc/codecs/tlv320aic32x4-clk.c
+++ b/sound/soc/codecs/tlv320aic32x4-clk.c
@@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
 	if (ret < 0)
 		return -EINVAL;
 
-	return clk_aic32x4_pll_set_muldiv(pll, &settings);
+	ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
+	if (ret)
+		return ret;
+
+	/* 10ms is the delay to wait before the clocks are stable */
+	msleep(10);
+
+	return 0;
 }
 
 static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
	Takashi Iwai <tiwai@suse.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
	alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH 1/3] ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization
Date: Fri, 11 Sep 2020 19:31:38 +0200	[thread overview]
Message-ID: <20200911173140.29984-2-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20200911173140.29984-1-miquel.raynal@bootlin.com>

As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.

The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 sound/soc/codecs/tlv320aic32x4-clk.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c
index 156c153c12ab..2f78e6820c75 100644
--- a/sound/soc/codecs/tlv320aic32x4-clk.c
+++ b/sound/soc/codecs/tlv320aic32x4-clk.c
@@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
 	if (ret < 0)
 		return -EINVAL;
 
-	return clk_aic32x4_pll_set_muldiv(pll, &settings);
+	ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
+	if (ret)
+		return ret;
+
+	/* 10ms is the delay to wait before the clocks are stable */
+	msleep(10);
+
+	return 0;
 }
 
 static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
-- 
2.20.1


  reply	other threads:[~2020-09-11 17:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11 17:31 [PATCH 0/3] tlv320aic3xx4 updates Miquel Raynal
2020-09-11 17:31 ` Miquel Raynal
2020-09-11 17:31 ` Miquel Raynal [this message]
2020-09-11 17:31   ` [PATCH 1/3] ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization Miquel Raynal
2020-09-11 17:31 ` [PATCH 2/3] ASoC: tlv320aic32x4: Fix bdiv clock rate derivation Miquel Raynal
2020-09-11 17:31   ` Miquel Raynal
2020-09-11 17:31 ` [PATCH 3/3] ASoC: tlv320aic32x4: Enable fast charge Miquel Raynal
2020-09-11 17:31   ` Miquel Raynal
2020-09-15  8:26   ` Alexandre Belloni
2020-09-15  8:26     ` Alexandre Belloni
2020-09-15 11:50     ` Mark Brown
2020-09-15 11:50       ` Mark Brown
2020-09-15 13:02       ` Alexandre Belloni
2020-09-15 13:02         ` Alexandre Belloni
2020-09-15 14:10         ` Mark Brown
2020-09-15 14:10           ` Mark Brown
2020-09-15 14:14           ` Miquel Raynal
2020-09-15 14:14             ` Miquel Raynal
2020-09-15 14:27             ` Alexandre Belloni
2020-09-15 14:27               ` Alexandre Belloni
2020-09-15 15:46               ` Mark Brown
2020-09-15 15:46                 ` Mark Brown
2020-09-21 21:40 ` [PATCH 0/3] tlv320aic3xx4 updates Mark Brown
2020-09-21 21:40   ` Mark Brown

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