From: Wenbin Mei <wenbin.mei@mediatek.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Chaotian Jing <chaotian.jing@mediatek.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
Wenbin Mei <wenbin.mei@mediatek.com>
Subject: [PATCH 2/3] arm64: dts: mt8192: add mmc device node
Date: Tue, 15 Sep 2020 13:58:34 +0800 [thread overview]
Message-ID: <20200915055835.25590-3-wenbin.mei@mediatek.com> (raw)
In-Reply-To: <20200915055835.25590-1-wenbin.mei@mediatek.com>
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&pio {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Wenbin Mei <wenbin.mei@mediatek.com>
Cc: devicetree@vger.kernel.org, Ulf Hansson <ulf.hansson@linaro.org>,
Wenbin Mei <wenbin.mei@mediatek.com>,
srv_heupstream@mediatek.com, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Chaotian Jing <chaotian.jing@mediatek.com>
Subject: [PATCH 2/3] arm64: dts: mt8192: add mmc device node
Date: Tue, 15 Sep 2020 13:58:34 +0800 [thread overview]
Message-ID: <20200915055835.25590-3-wenbin.mei@mediatek.com> (raw)
In-Reply-To: <20200915055835.25590-1-wenbin.mei@mediatek.com>
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&pio {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Wenbin Mei <wenbin.mei@mediatek.com>
Cc: devicetree@vger.kernel.org, Ulf Hansson <ulf.hansson@linaro.org>,
Wenbin Mei <wenbin.mei@mediatek.com>,
srv_heupstream@mediatek.com, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Chaotian Jing <chaotian.jing@mediatek.com>
Subject: [PATCH 2/3] arm64: dts: mt8192: add mmc device node
Date: Tue, 15 Sep 2020 13:58:34 +0800 [thread overview]
Message-ID: <20200915055835.25590-3-wenbin.mei@mediatek.com> (raw)
In-Reply-To: <20200915055835.25590-1-wenbin.mei@mediatek.com>
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&pio {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
--
2.18.0
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next prev parent reply other threads:[~2020-09-15 6:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-15 5:58 [PATCH 0/3] Add mmc support for MT8192 SoC Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` [PATCH 1/3] mmc: dt-bindings: add " Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei [this message]
2020-09-15 5:58 ` [PATCH 2/3] arm64: dts: mt8192: add mmc device node Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` [PATCH 3/3] mmc: mediatek: Add subsys clock control for MT8192 msdc Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
2020-09-15 5:58 ` Wenbin Mei
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