From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org
Cc: joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org,
robin.murphy@arm.com, baolu.lu@linux.intel.com,
Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com,
zhangfei.gao@linaro.org, xuzaibo@huawei.com,
fenghua.yu@intel.com, eric.auger@redhat.com,
Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: [PATCH v10 05/13] iommu/io-pgtable-arm: Move some definitions to a header
Date: Fri, 18 Sep 2020 12:18:45 +0200 [thread overview]
Message-ID: <20200918101852.582559-6-jean-philippe@linaro.org> (raw)
In-Reply-To: <20200918101852.582559-1-jean-philippe@linaro.org>
Extract some of the most generic TCR defines, so they can be reused by
the page table sharing code.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
drivers/iommu/io-pgtable-arm.h | 30 ++++++++++++++++++++++++++++++
drivers/iommu/io-pgtable-arm.c | 27 ++-------------------------
MAINTAINERS | 3 +--
3 files changed, 33 insertions(+), 27 deletions(-)
create mode 100644 drivers/iommu/io-pgtable-arm.h
diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h
new file mode 100644
index 000000000000..ba7cfdf7afa0
--- /dev/null
+++ b/drivers/iommu/io-pgtable-arm.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef IO_PGTABLE_ARM_H_
+#define IO_PGTABLE_ARM_H_
+
+#define ARM_LPAE_TCR_TG0_4K 0
+#define ARM_LPAE_TCR_TG0_64K 1
+#define ARM_LPAE_TCR_TG0_16K 2
+
+#define ARM_LPAE_TCR_TG1_16K 1
+#define ARM_LPAE_TCR_TG1_4K 2
+#define ARM_LPAE_TCR_TG1_64K 3
+
+#define ARM_LPAE_TCR_SH_NS 0
+#define ARM_LPAE_TCR_SH_OS 2
+#define ARM_LPAE_TCR_SH_IS 3
+
+#define ARM_LPAE_TCR_RGN_NC 0
+#define ARM_LPAE_TCR_RGN_WBWA 1
+#define ARM_LPAE_TCR_RGN_WT 2
+#define ARM_LPAE_TCR_RGN_WB 3
+
+#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
+#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
+#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
+#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
+#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
+#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
+#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+
+#endif /* IO_PGTABLE_ARM_H_ */
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dc7bcf858b6d..534810b6be77 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -20,6 +20,8 @@
#include <asm/barrier.h>
+#include "io-pgtable-arm.h"
+
#define ARM_LPAE_MAX_ADDR_BITS 52
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
#define ARM_LPAE_MAX_LEVELS 4
@@ -100,23 +102,6 @@
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
/* Register bits */
-#define ARM_LPAE_TCR_TG0_4K 0
-#define ARM_LPAE_TCR_TG0_64K 1
-#define ARM_LPAE_TCR_TG0_16K 2
-
-#define ARM_LPAE_TCR_TG1_16K 1
-#define ARM_LPAE_TCR_TG1_4K 2
-#define ARM_LPAE_TCR_TG1_64K 3
-
-#define ARM_LPAE_TCR_SH_NS 0
-#define ARM_LPAE_TCR_SH_OS 2
-#define ARM_LPAE_TCR_SH_IS 3
-
-#define ARM_LPAE_TCR_RGN_NC 0
-#define ARM_LPAE_TCR_RGN_WBWA 1
-#define ARM_LPAE_TCR_RGN_WT 2
-#define ARM_LPAE_TCR_RGN_WB 3
-
#define ARM_LPAE_VTCR_SL0_MASK 0x3
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
@@ -124,14 +109,6 @@
#define ARM_LPAE_VTCR_PS_SHIFT 16
#define ARM_LPAE_VTCR_PS_MASK 0x7
-#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
-#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
-#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
-#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
-#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
-#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
-#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
-
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d0862b19ce5..7b1bf8fda938 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1506,8 +1506,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/iommu/arm,smmu*
F: drivers/iommu/arm/
-F: drivers/iommu/io-pgtable-arm-v7s.c
-F: drivers/iommu/io-pgtable-arm.c
+F: drivers/iommu/io-pgtable-arm*
ARM SUB-ARCHITECTURES
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org
Cc: fenghua.yu@intel.com,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
catalin.marinas@arm.com, robin.murphy@arm.com,
zhangfei.gao@linaro.org, will@kernel.org
Subject: [PATCH v10 05/13] iommu/io-pgtable-arm: Move some definitions to a header
Date: Fri, 18 Sep 2020 12:18:45 +0200 [thread overview]
Message-ID: <20200918101852.582559-6-jean-philippe@linaro.org> (raw)
In-Reply-To: <20200918101852.582559-1-jean-philippe@linaro.org>
Extract some of the most generic TCR defines, so they can be reused by
the page table sharing code.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
drivers/iommu/io-pgtable-arm.h | 30 ++++++++++++++++++++++++++++++
drivers/iommu/io-pgtable-arm.c | 27 ++-------------------------
MAINTAINERS | 3 +--
3 files changed, 33 insertions(+), 27 deletions(-)
create mode 100644 drivers/iommu/io-pgtable-arm.h
diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h
new file mode 100644
index 000000000000..ba7cfdf7afa0
--- /dev/null
+++ b/drivers/iommu/io-pgtable-arm.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef IO_PGTABLE_ARM_H_
+#define IO_PGTABLE_ARM_H_
+
+#define ARM_LPAE_TCR_TG0_4K 0
+#define ARM_LPAE_TCR_TG0_64K 1
+#define ARM_LPAE_TCR_TG0_16K 2
+
+#define ARM_LPAE_TCR_TG1_16K 1
+#define ARM_LPAE_TCR_TG1_4K 2
+#define ARM_LPAE_TCR_TG1_64K 3
+
+#define ARM_LPAE_TCR_SH_NS 0
+#define ARM_LPAE_TCR_SH_OS 2
+#define ARM_LPAE_TCR_SH_IS 3
+
+#define ARM_LPAE_TCR_RGN_NC 0
+#define ARM_LPAE_TCR_RGN_WBWA 1
+#define ARM_LPAE_TCR_RGN_WT 2
+#define ARM_LPAE_TCR_RGN_WB 3
+
+#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
+#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
+#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
+#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
+#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
+#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
+#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+
+#endif /* IO_PGTABLE_ARM_H_ */
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dc7bcf858b6d..534810b6be77 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -20,6 +20,8 @@
#include <asm/barrier.h>
+#include "io-pgtable-arm.h"
+
#define ARM_LPAE_MAX_ADDR_BITS 52
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
#define ARM_LPAE_MAX_LEVELS 4
@@ -100,23 +102,6 @@
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
/* Register bits */
-#define ARM_LPAE_TCR_TG0_4K 0
-#define ARM_LPAE_TCR_TG0_64K 1
-#define ARM_LPAE_TCR_TG0_16K 2
-
-#define ARM_LPAE_TCR_TG1_16K 1
-#define ARM_LPAE_TCR_TG1_4K 2
-#define ARM_LPAE_TCR_TG1_64K 3
-
-#define ARM_LPAE_TCR_SH_NS 0
-#define ARM_LPAE_TCR_SH_OS 2
-#define ARM_LPAE_TCR_SH_IS 3
-
-#define ARM_LPAE_TCR_RGN_NC 0
-#define ARM_LPAE_TCR_RGN_WBWA 1
-#define ARM_LPAE_TCR_RGN_WT 2
-#define ARM_LPAE_TCR_RGN_WB 3
-
#define ARM_LPAE_VTCR_SL0_MASK 0x3
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
@@ -124,14 +109,6 @@
#define ARM_LPAE_VTCR_PS_SHIFT 16
#define ARM_LPAE_VTCR_PS_MASK 0x7
-#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
-#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
-#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
-#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
-#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
-#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
-#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
-
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d0862b19ce5..7b1bf8fda938 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1506,8 +1506,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/iommu/arm,smmu*
F: drivers/iommu/arm/
-F: drivers/iommu/io-pgtable-arm-v7s.c
-F: drivers/iommu/io-pgtable-arm.c
+F: drivers/iommu/io-pgtable-arm*
ARM SUB-ARCHITECTURES
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.28.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org
Cc: fenghua.yu@intel.com, jacob.jun.pan@linux.intel.com,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
catalin.marinas@arm.com, joro@8bytes.org, robin.murphy@arm.com,
eric.auger@redhat.com, Jonathan.Cameron@huawei.com,
zhangfei.gao@linaro.org, will@kernel.org, xuzaibo@huawei.com,
baolu.lu@linux.intel.com
Subject: [PATCH v10 05/13] iommu/io-pgtable-arm: Move some definitions to a header
Date: Fri, 18 Sep 2020 12:18:45 +0200 [thread overview]
Message-ID: <20200918101852.582559-6-jean-philippe@linaro.org> (raw)
In-Reply-To: <20200918101852.582559-1-jean-philippe@linaro.org>
Extract some of the most generic TCR defines, so they can be reused by
the page table sharing code.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
drivers/iommu/io-pgtable-arm.h | 30 ++++++++++++++++++++++++++++++
drivers/iommu/io-pgtable-arm.c | 27 ++-------------------------
MAINTAINERS | 3 +--
3 files changed, 33 insertions(+), 27 deletions(-)
create mode 100644 drivers/iommu/io-pgtable-arm.h
diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h
new file mode 100644
index 000000000000..ba7cfdf7afa0
--- /dev/null
+++ b/drivers/iommu/io-pgtable-arm.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef IO_PGTABLE_ARM_H_
+#define IO_PGTABLE_ARM_H_
+
+#define ARM_LPAE_TCR_TG0_4K 0
+#define ARM_LPAE_TCR_TG0_64K 1
+#define ARM_LPAE_TCR_TG0_16K 2
+
+#define ARM_LPAE_TCR_TG1_16K 1
+#define ARM_LPAE_TCR_TG1_4K 2
+#define ARM_LPAE_TCR_TG1_64K 3
+
+#define ARM_LPAE_TCR_SH_NS 0
+#define ARM_LPAE_TCR_SH_OS 2
+#define ARM_LPAE_TCR_SH_IS 3
+
+#define ARM_LPAE_TCR_RGN_NC 0
+#define ARM_LPAE_TCR_RGN_WBWA 1
+#define ARM_LPAE_TCR_RGN_WT 2
+#define ARM_LPAE_TCR_RGN_WB 3
+
+#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
+#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
+#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
+#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
+#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
+#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
+#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+
+#endif /* IO_PGTABLE_ARM_H_ */
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dc7bcf858b6d..534810b6be77 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -20,6 +20,8 @@
#include <asm/barrier.h>
+#include "io-pgtable-arm.h"
+
#define ARM_LPAE_MAX_ADDR_BITS 52
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
#define ARM_LPAE_MAX_LEVELS 4
@@ -100,23 +102,6 @@
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
/* Register bits */
-#define ARM_LPAE_TCR_TG0_4K 0
-#define ARM_LPAE_TCR_TG0_64K 1
-#define ARM_LPAE_TCR_TG0_16K 2
-
-#define ARM_LPAE_TCR_TG1_16K 1
-#define ARM_LPAE_TCR_TG1_4K 2
-#define ARM_LPAE_TCR_TG1_64K 3
-
-#define ARM_LPAE_TCR_SH_NS 0
-#define ARM_LPAE_TCR_SH_OS 2
-#define ARM_LPAE_TCR_SH_IS 3
-
-#define ARM_LPAE_TCR_RGN_NC 0
-#define ARM_LPAE_TCR_RGN_WBWA 1
-#define ARM_LPAE_TCR_RGN_WT 2
-#define ARM_LPAE_TCR_RGN_WB 3
-
#define ARM_LPAE_VTCR_SL0_MASK 0x3
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
@@ -124,14 +109,6 @@
#define ARM_LPAE_VTCR_PS_SHIFT 16
#define ARM_LPAE_VTCR_PS_MASK 0x7
-#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
-#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
-#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
-#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
-#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
-#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
-#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
-
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d0862b19ce5..7b1bf8fda938 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1506,8 +1506,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/iommu/arm,smmu*
F: drivers/iommu/arm/
-F: drivers/iommu/io-pgtable-arm-v7s.c
-F: drivers/iommu/io-pgtable-arm.c
+F: drivers/iommu/io-pgtable-arm*
ARM SUB-ARCHITECTURES
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.28.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-18 10:20 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-18 10:18 [PATCH v10 00/13] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 01/13] mm: Define pasid in mm Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-28 22:22 ` Will Deacon
2020-09-28 22:22 ` Will Deacon
2020-09-28 22:22 ` Will Deacon
2020-09-28 22:43 ` Fenghua Yu
2020-09-28 22:43 ` Fenghua Yu
2020-09-28 22:43 ` Fenghua Yu
2020-09-30 9:13 ` Jean-Philippe Brucker
2020-09-30 9:13 ` Jean-Philippe Brucker
2020-09-30 9:13 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 02/13] iommu/ioasid: Add ioasid references Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 03/13] iommu/sva: Add PASID helpers Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 04/13] arm64: mm: Pin down ASIDs for sharing mm with devices Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker [this message]
2020-09-18 10:18 ` [PATCH v10 05/13] iommu/io-pgtable-arm: Move some definitions to a header Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 06/13] arm64: cpufeature: Export symbol read_sanitised_ftr_reg() Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 07/13] iommu/arm-smmu-v3: Move definitions to a header Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 08/13] iommu/arm-smmu-v3: Share process page tables Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` [PATCH v10 09/13] iommu/arm-smmu-v3: Seize private ASID Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 13:07 ` Jonathan Cameron
2020-09-18 13:07 ` Jonathan Cameron
2020-09-18 13:07 ` Jonathan Cameron
2020-09-18 10:18 ` [PATCH v10 10/13] iommu/arm-smmu-v3: Check for SVA features Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-21 8:59 ` Shameerali Kolothum Thodi
2020-09-21 8:59 ` Shameerali Kolothum Thodi
2020-09-21 8:59 ` Shameerali Kolothum Thodi
2020-09-24 10:13 ` Jean-Philippe Brucker
2020-09-24 10:13 ` Jean-Philippe Brucker
2020-09-24 10:13 ` Jean-Philippe Brucker
2020-09-24 11:13 ` Shameerali Kolothum Thodi
2020-09-24 11:13 ` Shameerali Kolothum Thodi
2020-09-24 11:13 ` Shameerali Kolothum Thodi
2020-12-09 19:49 ` Krishna Reddy
2020-12-09 19:49 ` Krishna Reddy
2020-12-09 19:49 ` Krishna Reddy
2020-12-09 20:07 ` Will Deacon
2020-12-09 20:07 ` Will Deacon
2020-12-09 20:07 ` Will Deacon
2020-12-09 20:38 ` Krishna Reddy
2020-12-09 20:38 ` Krishna Reddy
2020-12-09 20:38 ` Krishna Reddy
2020-12-14 9:32 ` Jean-Philippe Brucker
2020-12-14 9:32 ` Jean-Philippe Brucker
2020-12-14 9:32 ` Jean-Philippe Brucker
2020-12-14 23:23 ` Krishna Reddy
2020-12-14 23:23 ` Krishna Reddy
2020-12-14 23:23 ` Krishna Reddy
2020-09-18 10:18 ` [PATCH v10 11/13] iommu/arm-smmu-v3: Add SVA device feature Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-12-15 1:09 ` Krishna Reddy
2020-12-15 1:09 ` Krishna Reddy
2020-12-15 1:09 ` Krishna Reddy
2021-01-06 10:09 ` Jean-Philippe Brucker
2021-01-06 10:09 ` Jean-Philippe Brucker
2021-01-06 10:09 ` Jean-Philippe Brucker
2021-01-06 17:23 ` Krishna Reddy
2021-01-06 17:23 ` Krishna Reddy
2021-01-06 17:23 ` Krishna Reddy
2020-09-18 10:18 ` [PATCH v10 12/13] iommu/arm-smmu-v3: Implement iommu_sva_bind/unbind() Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-11-24 23:58 ` Jason Gunthorpe
2020-11-24 23:58 ` Jason Gunthorpe
2020-11-24 23:58 ` Jason Gunthorpe
2020-11-25 9:27 ` Jean-Philippe Brucker
2020-11-25 9:27 ` Jean-Philippe Brucker
2020-11-25 9:27 ` Jean-Philippe Brucker
2020-11-26 0:37 ` Jason Gunthorpe
2020-11-26 0:37 ` Jason Gunthorpe
2020-11-26 0:37 ` Jason Gunthorpe
2020-09-18 10:18 ` [PATCH v10 13/13] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 10:18 ` Jean-Philippe Brucker
2020-09-18 13:15 ` [PATCH v10 00/13] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Jonathan Cameron
2020-09-18 13:15 ` Jonathan Cameron
2020-09-18 13:15 ` Jonathan Cameron
2020-09-28 16:47 ` Jean-Philippe Brucker
2020-09-28 16:47 ` Jean-Philippe Brucker
2020-09-28 16:47 ` Jean-Philippe Brucker
2020-09-28 17:23 ` Will Deacon
2020-09-28 17:23 ` Will Deacon
2020-09-28 17:23 ` Will Deacon
2020-09-28 22:39 ` Will Deacon
2020-09-28 22:39 ` Will Deacon
2020-09-28 22:39 ` Will Deacon
2020-09-30 9:12 ` Jean-Philippe Brucker
2020-09-30 9:12 ` Jean-Philippe Brucker
2020-09-30 9:12 ` Jean-Philippe Brucker
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