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From: Maxime Ripard <maxime@cerno.tech>
To: Eric Anholt <eric@anholt.net>
Cc: Tim Gover <tim.gover@raspberrypi.com>,
	Dave Stevenson <dave.stevenson@raspberrypi.com>,
	dri-devel@lists.freedesktop.org,
	bcm-kernel-feedback-list@broadcom.com,
	linux-rpi-kernel@lists.infradead.org,
	Phil Elwell <phil@raspberrypi.com>,
	linux-arm-kernel@lists.infradead.org,
	Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH 1/2] drm/vc4: kms: Assign a FIFO to enabled CRTCs instead of active
Date: Fri, 18 Sep 2020 16:59:17 +0200	[thread overview]
Message-ID: <20200918145918.101068-1-maxime@cerno.tech> (raw)

The HVS has three FIFOs that can be assigned to a number of PixelValves
through a mux.

However, changing that FIFO requires that we disable and then enable the
pixelvalve, so we want to assign FIFOs to all the enabled CRTCs, and not
just the active ones.

Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index af3ee3dcdab6..01fa60844695 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -643,7 +643,7 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 		struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 		unsigned int matching_channels;
 
-		if (!crtc_state->active)
+		if (!crtc_state->enable)
 			continue;
 
 		/*
-- 
2.26.2


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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime@cerno.tech>
To: Eric Anholt <eric@anholt.net>
Cc: Tim Gover <tim.gover@raspberrypi.com>,
	Dave Stevenson <dave.stevenson@raspberrypi.com>,
	dri-devel@lists.freedesktop.org,
	bcm-kernel-feedback-list@broadcom.com,
	linux-rpi-kernel@lists.infradead.org,
	Phil Elwell <phil@raspberrypi.com>,
	linux-arm-kernel@lists.infradead.org,
	Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH 1/2] drm/vc4: kms: Assign a FIFO to enabled CRTCs instead of active
Date: Fri, 18 Sep 2020 16:59:17 +0200	[thread overview]
Message-ID: <20200918145918.101068-1-maxime@cerno.tech> (raw)

The HVS has three FIFOs that can be assigned to a number of PixelValves
through a mux.

However, changing that FIFO requires that we disable and then enable the
pixelvalve, so we want to assign FIFOs to all the enabled CRTCs, and not
just the active ones.

Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index af3ee3dcdab6..01fa60844695 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -643,7 +643,7 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 		struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 		unsigned int matching_channels;
 
-		if (!crtc_state->active)
+		if (!crtc_state->enable)
 			continue;
 
 		/*
-- 
2.26.2

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

             reply	other threads:[~2020-09-18 15:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20200919084635epcas1p3b36b85b4445709cf3595fc62e659c1ae@epcas1p3.samsung.com>
2020-09-18 14:59 ` Maxime Ripard [this message]
2020-09-18 14:59   ` [PATCH 1/2] drm/vc4: kms: Assign a FIFO to enabled CRTCs instead of active Maxime Ripard
2020-09-18 14:59   ` [PATCH 2/2] drm/vc4: crtc: Keep the previously assigned HVS FIFO Maxime Ripard
2020-09-18 14:59     ` Maxime Ripard
2020-09-18 16:46     ` Dave Stevenson
2020-09-18 16:46       ` Dave Stevenson
2020-09-18 15:43   ` [PATCH 1/2] drm/vc4: kms: Assign a FIFO to enabled CRTCs instead of active Dave Stevenson
2020-09-18 15:43     ` Dave Stevenson
2020-09-23  8:27     ` Maxime Ripard
2020-09-23  8:27       ` Maxime Ripard
2020-09-24  8:08   ` Hoegeun Kwon
2020-09-24  8:08     ` Hoegeun Kwon
2020-09-30 12:08     ` Maxime Ripard
2020-09-30 12:08       ` Maxime Ripard
2020-10-01 15:04     ` Maxime Ripard
2020-10-01 15:04       ` Maxime Ripard

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