From: Zhen Lei <thunder.leizhen@huawei.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, "Alexey Brodkin" <abrodkin@synopsys.com>, Vineet Gupta <vgupta@synopsys.com>, devicetree <devicetree@vger.kernel.org>, linux-snps-arc <linux-snps-arc@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org> Cc: Zhen Lei <thunder.leizhen@huawei.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Haoyu Lv <lvhaoyu@huawei.com>, Libin <huawei.libin@huawei.com>, Kefeng Wang <wangkefeng.wang@huawei.com> Subject: [PATCH v6 3/6] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Thu, 24 Sep 2020 15:17:51 +0800 [thread overview] Message-ID: <20200924071754.4509-4-thunder.leizhen@huawei.com> (raw) In-Reply-To: <20200924071754.4509-1-thunder.leizhen@huawei.com> Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 74 ++++++++++++++++++++++++++++++++++----- 2 files changed, 67 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc31c..7c2d1c8fa551a66 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 5458004242e9d20..418183b9983dfad 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include <linux/irqchip/chained_irq.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/interrupt.h> #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,27 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* irq domain of the primary interrupt controller. */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~BIT(hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +72,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -75,13 +121,20 @@ static int __init dw_apb_ictl_init(struct device_node *np, void __iomem *iobase; int ret, nrirqs, parent_irq, i; u32 reg; - const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; - - /* Map the parent interrupt for the chained handler */ - parent_irq = irq_of_parse_and_map(np, 0); - if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + const struct irq_domain_ops *domain_ops; + + if (!parent || (np == parent)) { + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + } else { + /* Map the parent interrupt for the chained handler */ + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + domain_ops = &irq_generic_chip_ops; } ret = of_address_to_resource(np, 0, &r); @@ -146,8 +199,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0; -- 1.8.3
WARNING: multiple messages have this Message-ID (diff)
From: Zhen Lei <thunder.leizhen@huawei.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, "Alexey Brodkin" <abrodkin@synopsys.com>, Vineet Gupta <vgupta@synopsys.com>, devicetree <devicetree@vger.kernel.org>, linux-snps-arc <linux-snps-arc@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org> Cc: Haoyu Lv <lvhaoyu@huawei.com>, Kefeng Wang <wangkefeng.wang@huawei.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Libin <huawei.libin@huawei.com>, Zhen Lei <thunder.leizhen@huawei.com> Subject: [PATCH v6 3/6] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Thu, 24 Sep 2020 15:17:51 +0800 [thread overview] Message-ID: <20200924071754.4509-4-thunder.leizhen@huawei.com> (raw) In-Reply-To: <20200924071754.4509-1-thunder.leizhen@huawei.com> Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 74 ++++++++++++++++++++++++++++++++++----- 2 files changed, 67 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc31c..7c2d1c8fa551a66 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 5458004242e9d20..418183b9983dfad 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include <linux/irqchip/chained_irq.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/interrupt.h> #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,27 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* irq domain of the primary interrupt controller. */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~BIT(hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +72,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -75,13 +121,20 @@ static int __init dw_apb_ictl_init(struct device_node *np, void __iomem *iobase; int ret, nrirqs, parent_irq, i; u32 reg; - const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; - - /* Map the parent interrupt for the chained handler */ - parent_irq = irq_of_parse_and_map(np, 0); - if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + const struct irq_domain_ops *domain_ops; + + if (!parent || (np == parent)) { + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + } else { + /* Map the parent interrupt for the chained handler */ + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + domain_ops = &irq_generic_chip_ops; } ret = of_address_to_resource(np, 0, &r); @@ -146,8 +199,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0; -- 1.8.3 _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
next prev parent reply other threads:[~2020-09-24 7:19 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-24 7:17 [PATCH v6 0/6] irqchip: dw-apb-ictl: support hierarchy irq domain Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-09-24 7:17 ` [PATCH v6 1/6] genirq: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-10-11 17:57 ` [tip: irq/core] genirq: Add stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER tip-bot2 for Zhen Lei 2020-09-24 7:17 ` [PATCH v6 2/6] irqchip: dw-apb-ictl: prepare for support hierarchy irq domain Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-10-11 17:57 ` [tip: irq/core] irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains tip-bot2 for Zhen Lei 2020-09-24 7:17 ` Zhen Lei [this message] 2020-09-24 7:17 ` [PATCH v6 3/6] irqchip: dw-apb-ictl: support hierarchy irq domain Zhen Lei 2020-10-11 17:57 ` [tip: irq/core] irqchip/dw-apb-ictl: Add primary interrupt controller support tip-bot2 for Zhen Lei 2020-09-24 7:17 ` [PATCH v6 4/6] dt-bindings: dw-apb-ictl: support hierarchy irq domain Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-10-11 17:57 ` [tip: irq/core] dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller tip-bot2 for Zhen Lei 2020-09-24 7:17 ` [PATCH v6 5/6] dt-bindings: dw-apb-ictl: convert to json-schema Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-09-27 9:53 ` Leizhen (ThunderTown) 2020-09-27 9:53 ` Leizhen (ThunderTown) 2020-09-28 18:26 ` Rob Herring 2020-09-28 18:26 ` Rob Herring 2020-09-29 1:37 ` Leizhen (ThunderTown) 2020-09-29 1:37 ` Leizhen (ThunderTown) 2020-09-24 7:17 ` [PATCH v6 6/6] ARC: [dts] fix the errors detected by dtbs_check Zhen Lei 2020-09-24 7:17 ` Zhen Lei 2020-09-28 18:32 ` Vineet Gupta 2020-09-28 18:32 ` Vineet Gupta 2020-09-25 15:54 ` [PATCH v6 0/6] irqchip: dw-apb-ictl: support hierarchy irq domain Marc Zyngier 2020-09-25 15:54 ` Marc Zyngier 2020-09-27 6:49 ` Leizhen (ThunderTown) 2020-09-27 6:49 ` Leizhen (ThunderTown)
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