From: Alexandru Elisei <alexandru.elisei@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, sumit.garg@linaro.org, maz@kernel.org, swboyd@chromium.org, catalin.marinas@arm.com, will@kernel.org, Julien Thierry <julien.thierry.kdev@gmail.com>, Will Deacon <will.deacon@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>, Julien Thierry <julien.thierry@arm.com> Subject: [PATCH v7 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_counter() Date: Thu, 24 Sep 2020 12:07:00 +0100 [thread overview] Message-ID: <20200924110706.254996-2-alexandru.elisei@arm.com> (raw) In-Reply-To: <20200924110706.254996-1-alexandru.elisei@arm.com> Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In armv8pmu_enable_event(), the PE can reorder configuring the event type after we have enabled the counter and the interrupt. This can lead to an interrupt being asserted because of the previous event type that we were counting using the same counter, not the one that we've just configured. The same rationale applies to writes to the PMINTENSET_EL1 register. The PE can reorder enabling the interrupt at any point in the future after we have enabled the event. Prevent both situations from happening by adding an ISB just before we enable the event counter. Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Fixes: 030896885ade ("arm64: Performance counters support") Reported-by: Julien Thierry <julien.thierry@arm.com> Tested-by: Sumit Garg <sumit.garg@linaro.org> (Developerbox) Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- arch/arm64/kernel/perf_event.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 462f9a9cc44b..481d48e3872b 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -532,6 +532,11 @@ static u32 armv8pmu_event_cnten_mask(struct perf_event *event) static inline void armv8pmu_enable_counter(u32 mask) { + /* + * Make sure event configuration register writes are visible before we + * enable the counter. + * */ + isb(); write_sysreg(mask, pmcntenset_el0); } -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, sumit.garg@linaro.org, Julien Thierry <julien.thierry@arm.com>, Peter Zijlstra <peterz@infradead.org>, catalin.marinas@arm.com, Jiri Olsa <jolsa@redhat.com>, Will Deacon <will.deacon@arm.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, swboyd@chromium.org, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Ingo Molnar <mingo@redhat.com>, maz@kernel.org, Namhyung Kim <namhyung@kernel.org>, will@kernel.org, Julien Thierry <julien.thierry.kdev@gmail.com> Subject: [PATCH v7 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_counter() Date: Thu, 24 Sep 2020 12:07:00 +0100 [thread overview] Message-ID: <20200924110706.254996-2-alexandru.elisei@arm.com> (raw) In-Reply-To: <20200924110706.254996-1-alexandru.elisei@arm.com> Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In armv8pmu_enable_event(), the PE can reorder configuring the event type after we have enabled the counter and the interrupt. This can lead to an interrupt being asserted because of the previous event type that we were counting using the same counter, not the one that we've just configured. The same rationale applies to writes to the PMINTENSET_EL1 register. The PE can reorder enabling the interrupt at any point in the future after we have enabled the event. Prevent both situations from happening by adding an ISB just before we enable the event counter. Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Fixes: 030896885ade ("arm64: Performance counters support") Reported-by: Julien Thierry <julien.thierry@arm.com> Tested-by: Sumit Garg <sumit.garg@linaro.org> (Developerbox) Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- arch/arm64/kernel/perf_event.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 462f9a9cc44b..481d48e3872b 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -532,6 +532,11 @@ static u32 armv8pmu_event_cnten_mask(struct perf_event *event) static inline void armv8pmu_enable_counter(u32 mask) { + /* + * Make sure event configuration register writes are visible before we + * enable the counter. + * */ + isb(); write_sysreg(mask, pmcntenset_el0); } -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-24 11:06 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-24 11:06 [PATCH v7 0/7] arm_pmu: Use NMI for perf interrupt Alexandru Elisei 2020-09-24 11:06 ` Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei [this message] 2020-09-24 11:07 ` [PATCH v7 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_counter() Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 2/7] arm64: perf: Avoid PMXEV* indirection Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 3/7] arm64: perf: Remove PMU locking Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 4/7] arm64: perf: Defer irq_work to IPI_IRQ_WORK Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 5/7] KVM: arm64: pmu: Make overflow handler NMI safe Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-28 17:57 ` Will Deacon 2020-09-28 17:57 ` Will Deacon 2020-09-28 17:57 ` Will Deacon 2020-09-30 12:37 ` Alexandru Elisei 2020-09-30 12:37 ` Alexandru Elisei 2020-09-30 12:37 ` Alexandru Elisei 2020-09-29 8:11 ` Marc Zyngier 2020-09-29 8:11 ` Marc Zyngier 2020-09-29 8:11 ` Marc Zyngier 2020-09-30 11:46 ` Alexandru Elisei 2020-09-30 11:46 ` Alexandru Elisei 2020-09-30 11:46 ` Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 6/7] arm_pmu: Introduce pmu_irq_ops Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-24 11:07 ` [PATCH v7 7/7] arm_pmu: arm64: Use NMIs for PMU Alexandru Elisei 2020-09-24 11:07 ` Alexandru Elisei 2020-09-28 22:13 ` [PATCH v7 0/7] arm_pmu: Use NMI for perf interrupt Will Deacon 2020-09-28 22:13 ` Will Deacon
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