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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 25/25] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register
Date: Mon, 28 Sep 2020 10:35:13 -0600	[thread overview]
Message-ID: <20200928163513.70169-26-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200928163513.70169-1-mathieu.poirier@linaro.org>

From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 state variable which is used to
store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index de76d57850bc..abd706b216ac 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1243,7 +1243,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
 
 	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
-	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
+	state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1);
 
 	state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
 
@@ -1353,7 +1353,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
 
 	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
-	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
+	writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1);
 
 	writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
 
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 25/25] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register
Date: Mon, 28 Sep 2020 10:35:13 -0600	[thread overview]
Message-ID: <20200928163513.70169-26-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200928163513.70169-1-mathieu.poirier@linaro.org>

From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 state variable which is used to
store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index de76d57850bc..abd706b216ac 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1243,7 +1243,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
 
 	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
-	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
+	state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1);
 
 	state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
 
@@ -1353,7 +1353,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
 
 	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
-	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
+	writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1);
 
 	writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
 
-- 
2.25.1


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  parent reply	other threads:[~2020-09-28 16:35 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-28 16:34 [PATCH 00/25] coresight: Next v5.9-rc7 Mathieu Poirier
2020-09-28 16:34 ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 01/25] coresight: cpu_debug: Add module name in Kconfig Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 02/25] coresight: cpu_debug: Define MODULE_DEVICE_TABLE Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 03/25] coresight: Use IS_ENABLED for CONFIGs that may be modules Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 04/25] coresight: Add coresight prefix to barrier_pkt Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 05/25] coresight: Export global symbols Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 06/25] coresight: Add try_get_module() in coresight_grab_device() Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 07/25] coresight: stm: Allow to build coresight-stm as a module Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 08/25] coresight: etm: perf: Fix warning caused by etm_setup_aux failure Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 09/25] coresight: etm3x: Allow etm3x to be built as a module Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 10/25] coresight: etm4x: Allow etm4x " Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:34 ` [PATCH 11/25] coresight: etb: Allow etb " Mathieu Poirier
2020-09-28 16:34   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 12/25] coresight: tpiu: Allow tpiu " Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 13/25] coresight: tmc: Allow tmc " Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 14/25] coresight: funnel: Allow funnel driver to be built as module Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 15/25] coresight: replicator: Allow replicator " Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 16/25] coresight: cti: Add function to register cti associate ops Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 17/25] coresight: cti: Fix remove sysfs link error Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 18/25] coresight: cti: Fix bug clearing sysfs links on callback Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 19/25] coresight: cti: Don't disable ect device if it's not enabled Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 20/25] coresight: cti: Increase reference count when enabling cti Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 21/25] coresight: cti: Allow cti to be built as a module Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 22/25] coresight: tmc-etr: Add function to register catu ops Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 23/25] coresight: catu: Allow catu drivers to be built as modules Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` [PATCH 24/25] coresight: core: Allow the coresight core driver to be built as a module Mathieu Poirier
2020-09-28 16:35   ` Mathieu Poirier
2020-09-28 16:35 ` Mathieu Poirier [this message]
2020-09-28 16:35   ` [PATCH 25/25] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register Mathieu Poirier

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