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From: Luc Michel <luc@lmichel.fr>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Luc Michel" <luc@lmichel.fr>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Andrew Baumann" <Andrew.Baumann@microsoft.com>,
	"Paul Zimmerman" <pauldzim@gmail.com>,
	"Niek Linnenbank" <nieklinnenbank@gmail.com>,
	qemu-arm@nongnu.org, "Havard Skinnemoen" <hskinnemoen@google.com>
Subject: [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour
Date: Mon,  5 Oct 2020 21:56:06 +0200	[thread overview]
Message-ID: <20201005195612.1999165-10-luc@lmichel.fr> (raw)
In-Reply-To: <20201005195612.1999165-1-luc@lmichel.fr>

A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
---
 hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
index 12fa78181b..71c1d7b9e7 100644
--- a/hw/misc/bcm2835_cprman.c
+++ b/hw/misc/bcm2835_cprman.c
@@ -132,13 +132,44 @@ static const TypeInfo cprman_pll_info = {
 };
 
 
 /* PLL channel */
 
+static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
+{
+    /*
+     * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
+     * not set it when enabling the channel, but does clear it when disabling
+     * it.
+     */
+    return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
+        && !(*channel->reg_cm & channel->hold_mask);
+}
+
 static void pll_channel_update(CprmanPllChannelState *channel)
 {
-    clock_update(channel->out, 0);
+    uint64_t freq, div;
+
+    if (!pll_channel_is_enabled(channel)) {
+        clock_update(channel->out, 0);
+        return;
+    }
+
+    div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
+
+    if (!div) {
+        /*
+         * It seems that when the divider value is 0, it is considered as
+         * being maximum by the hardware (see the Linux driver).
+         */
+        div = R_A2W_PLLx_CHANNELy_DIV_MASK;
+    }
+
+    /* Some channels have an additional fixed divider */
+    freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
+
+    clock_update_hz(channel->out, freq);
 }
 
 /* Update a PLL and all its channels */
 static void pll_update_all_channels(BCM2835CprmanState *s,
                                     CprmanPllState *pll)
-- 
2.28.0



  parent reply	other threads:[~2020-10-05 20:34 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-05 19:55 [PATCH v2 00/15] raspi: add the bcm2835 cprman clock manager Luc Michel
2020-10-05 19:55 ` [PATCH v2 01/15] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro Luc Michel
2020-10-05 19:55 ` [PATCH v2 02/15] hw/core/clock: trace clock values in Hz instead of ns Luc Michel
2020-10-05 19:56 ` [PATCH v2 03/15] hw/core/clock: add the clock_new helper function Luc Michel
2020-10-06  9:10   ` Philippe Mathieu-Daudé
2020-10-05 19:56 ` [PATCH v2 04/15] hw/arm/raspi: fix CPRMAN base address Luc Michel
2020-10-05 19:56 ` [PATCH v2 05/15] hw/arm/raspi: add a skeleton implementation of the CPRMAN Luc Michel
2020-10-05 19:56 ` [PATCH v2 06/15] hw/misc/bcm2835_cprman: add a PLL skeleton implementation Luc Michel
2020-10-05 19:56 ` [PATCH v2 07/15] hw/misc/bcm2835_cprman: implement PLLs behaviour Luc Michel
2020-10-05 19:56 ` [PATCH v2 08/15] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation Luc Michel
2020-10-05 19:56 ` Luc Michel [this message]
2020-10-06  9:07   ` [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour Philippe Mathieu-Daudé
2020-10-05 19:56 ` [PATCH v2 10/15] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation Luc Michel
2020-10-06  8:40   ` Philippe Mathieu-Daudé
2020-10-10 11:33     ` Luc Michel
2020-10-10 11:50       ` Luc Michel
2020-10-05 19:56 ` [PATCH v2 11/15] hw/misc/bcm2835_cprman: implement clock mux behaviour Luc Michel
2020-10-06  9:04   ` Philippe Mathieu-Daudé
2020-10-10 13:09     ` Luc Michel
2020-10-05 19:56 ` [PATCH v2 12/15] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer Luc Michel
2020-10-05 19:56 ` [PATCH v2 13/15] hw/misc/bcm2835_cprman: add sane reset values to the registers Luc Michel
2020-10-19 15:39   ` Philippe Mathieu-Daudé
2020-10-05 19:56 ` [PATCH v2 14/15] hw/char/pl011: add a clock input Luc Michel
2020-10-05 19:56 ` [PATCH v2 15/15] hw/arm/bcm2835_peripherals: connect the UART clock Luc Michel
2020-10-06  9:05   ` Philippe Mathieu-Daudé

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