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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Mark Brown <broonie@kernel.org>, Serge Semin <fancer.lancer@gmail.com>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Andy Shevchenko <andy.shevchenko@gmail.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Lars Povlsen <lars.povlsen@microchip.com>,
	"wuxu . wu" <wuxu.wu@huawei.com>, Feng Tang <feng.tang@intel.com>,
	Rob Herring <robh+dt@kernel.org>, <linux-spi@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v4 10/21] spi: dw: Perform IRQ setup in a dedicated function
Date: Thu, 8 Oct 2020 02:54:59 +0300	[thread overview]
Message-ID: <20201007235511.4935-11-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20201007235511.4935-1-Sergey.Semin@baikalelectronics.ru>

In order to make the transfer_one() callback method more readable and
for unification with the DMA-based transfer, let's detach the IRQ setup
procedure into a dedicated function. While at it rename the IRQ-based
transfer handler function to be dw_spi-prefixe and looking more like the
DMA-related one.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 drivers/spi/spi-dw-core.c | 41 ++++++++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 4a45610c85f1..e7ffcfff6594 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -178,7 +178,7 @@ static void int_error_stop(struct dw_spi *dws, const char *msg)
 	spi_finalize_current_transfer(dws->master);
 }
 
-static irqreturn_t interrupt_transfer(struct dw_spi *dws)
+static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
 {
 	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 
@@ -315,6 +315,27 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
 }
 EXPORT_SYMBOL_GPL(dw_spi_update_config);
 
+static void dw_spi_irq_setup(struct dw_spi *dws)
+{
+	u16 level;
+	u8 imask;
+
+	/*
+	 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
+	 * will be adjusted at the final stage of the IRQ-based SPI transfer
+	 * execution so not to lose the leftover of the incoming data.
+	 */
+	level = min_t(u16, dws->fifo_len / 2, dws->tx_len);
+	dw_writel(dws, DW_SPI_TXFTLR, level);
+	dw_writel(dws, DW_SPI_RXFTLR, level - 1);
+
+	imask = SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI |
+		SPI_INT_RXFI;
+	spi_umask_intr(dws, imask);
+
+	dws->transfer_handler = dw_spi_transfer_handler;
+}
+
 static int dw_spi_transfer_one(struct spi_controller *master,
 		struct spi_device *spi, struct spi_transfer *transfer)
 {
@@ -324,8 +345,6 @@ static int dw_spi_transfer_one(struct spi_controller *master,
 		.dfs = transfer->bits_per_word,
 		.freq = transfer->speed_hz,
 	};
-	u8 imask = 0;
-	u16 txlevel = 0;
 	int ret;
 
 	dws->dma_mapped = 0;
@@ -358,21 +377,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
 			return ret;
 		}
 	} else {
-		/*
-		 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
-		 * will be adjusted at the final stage of the IRQ-based SPI transfer
-		 * execution so not to lose the leftover of the incoming data.
-		 */
-		txlevel = min_t(u16, dws->fifo_len / 2, dws->tx_len);
-		dw_writel(dws, DW_SPI_TXFTLR, txlevel);
-		dw_writel(dws, DW_SPI_RXFTLR, txlevel - 1);
-
-		/* Set the interrupt mask */
-		imask |= SPI_INT_TXEI | SPI_INT_TXOI |
-			 SPI_INT_RXUI | SPI_INT_RXOI | SPI_INT_RXFI;
-		spi_umask_intr(dws, imask);
-
-		dws->transfer_handler = interrupt_transfer;
+		dw_spi_irq_setup(dws);
 	}
 
 	spi_enable_chip(dws, 1);
-- 
2.27.0


  parent reply	other threads:[~2020-10-07 23:55 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-07 23:54 [PATCH v4 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support Serge Semin
2020-10-07 23:54 ` [PATCH v4 01/21] spi: dw: Use an explicit set_cs assignment Serge Semin
2020-10-07 23:54 ` [PATCH v4 02/21] spi: dw: Add DWC SSI capability Serge Semin
2020-10-07 23:54 ` [PATCH v4 03/21] spi: dw: Detach SPI device specific CR0 config method Serge Semin
2020-10-07 23:54 ` [PATCH v4 04/21] spi: dw: Update SPI bus speed in a config function Serge Semin
2020-10-07 23:54 ` [PATCH v4 05/21] spi: dw: Simplify the SPI bus speed config procedure Serge Semin
2020-10-07 23:54 ` [PATCH v4 06/21] spi: dw: Update Rx sample delay in the config function Serge Semin
2020-10-07 23:54 ` [PATCH v4 07/21] spi: dw: Add DW SPI controller config structure Serge Semin
2020-10-07 23:54 ` [PATCH v4 08/21] spi: dw: Refactor data IO procedure Serge Semin
2020-10-07 23:54 ` [PATCH v4 09/21] spi: dw: Refactor IRQ-based SPI transfer procedure Serge Semin
2020-10-07 23:54 ` Serge Semin [this message]
2020-10-07 23:55 ` [PATCH v4 11/21] spi: dw: Unmask IRQs after enabling the chip Serge Semin
2020-10-07 23:55 ` [PATCH v4 12/21] spi: dw: Discard chip enabling on DMA setup error Serge Semin
2020-10-07 23:55 ` [PATCH v4 13/21] spi: dw: De-assert chip-select on reset Serge Semin
2020-10-07 23:55 ` [PATCH v4 14/21] spi: dw: Explicitly de-assert CS on SPI transfer completion Serge Semin
2020-10-07 23:55 ` [PATCH v4 15/21] spi: dw: Move num-of retries parameter to the header file Serge Semin
2020-10-07 23:55 ` [PATCH v4 16/21] spi: dw: Add generic DW SSI status-check method Serge Semin
2020-10-07 23:55 ` [PATCH v4 17/21] spi: dw: Add memory operations support Serge Semin
2020-10-07 23:55 ` [PATCH v4 18/21] spi: dw: Introduce max mem-ops SPI bus frequency setting Serge Semin
2020-10-07 23:55 ` [PATCH v4 19/21] spi: dw: Add poll-based SPI transfers support Serge Semin
2020-10-07 23:55 ` [PATCH v4 20/21] dt-bindings: spi: dw: Add Baikal-T1 SPI Controllers Serge Semin
2020-10-07 23:55 ` [PATCH v4 21/21] spi: dw: Add Baikal-T1 SPI Controller glue driver Serge Semin
2020-10-08 22:02 ` [PATCH v4 00/21] spi: dw: Add full Baikal-T1 SPI Controllers support Mark Brown

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