From: Elaine Zhang <zhangqing@rock-chips.com> To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang <zhangqing@rock-chips.com> Subject: [PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq Date: Wed, 14 Oct 2020 10:28:11 +0800 [thread overview] Message-ID: <20201014022812.6733-5-zhangqing@rock-chips.com> (raw) In-Reply-To: <20201014022812.6733-1-zhangqing@rock-chips.com> set pll sequence: ->set pll to slow mode or other plls ->set pll down ->set pll params ->set pll up ->wait pll lock status ->set pll to normal mode To slove the system error: wait_pll_lock: timeout waiting for pll to lock pll_set_params: pll update unsucessful, trying to restore old params Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-pll.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 4c6c9167ef50..8adc6f54a605 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -210,6 +210,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, rate_change_remuxed = 1; } + /* set pll power down */ + writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, + RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + /* update pll values */ writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, RK3036_PLLCON0_FBDIV_SHIFT) | @@ -231,6 +236,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); + /* set pll power up */ + writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + udelay(1); + /* wait for the pll to lock */ ret = rockchip_rk3036_pll_wait_lock(pll); if (ret) { @@ -692,6 +702,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, rate_change_remuxed = 1; } + /* set pll power down */ + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + /* update pll values */ writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, RK3399_PLLCON0_FBDIV_SHIFT), @@ -715,6 +730,12 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, RK3399_PLLCON3_DSMPD_SHIFT), pll->reg_base + RK3399_PLLCON(3)); + /* set pll power up */ + writel(HIWORD_UPDATE(0, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + udelay(1); + /* wait for the pll to lock */ ret = rockchip_rk3399_pll_wait_lock(pll); if (ret) { -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Elaine Zhang <zhangqing@rock-chips.com> To: heiko@sntech.de Cc: huangtao@rock-chips.com, xf@rock-chips.com, sboyd@kernel.org, mturquette@baylibre.com, Elaine Zhang <zhangqing@rock-chips.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kever.yang@rock-chips.com, linux-rockchip@lists.infradead.org, xxx@rock-chips.com Subject: [PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq Date: Wed, 14 Oct 2020 10:28:11 +0800 [thread overview] Message-ID: <20201014022812.6733-5-zhangqing@rock-chips.com> (raw) In-Reply-To: <20201014022812.6733-1-zhangqing@rock-chips.com> set pll sequence: ->set pll to slow mode or other plls ->set pll down ->set pll params ->set pll up ->wait pll lock status ->set pll to normal mode To slove the system error: wait_pll_lock: timeout waiting for pll to lock pll_set_params: pll update unsucessful, trying to restore old params Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-pll.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 4c6c9167ef50..8adc6f54a605 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -210,6 +210,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, rate_change_remuxed = 1; } + /* set pll power down */ + writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, + RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + /* update pll values */ writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, RK3036_PLLCON0_FBDIV_SHIFT) | @@ -231,6 +236,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); + /* set pll power up */ + writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + udelay(1); + /* wait for the pll to lock */ ret = rockchip_rk3036_pll_wait_lock(pll); if (ret) { @@ -692,6 +702,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, rate_change_remuxed = 1; } + /* set pll power down */ + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + /* update pll values */ writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, RK3399_PLLCON0_FBDIV_SHIFT), @@ -715,6 +730,12 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, RK3399_PLLCON3_DSMPD_SHIFT), pll->reg_base + RK3399_PLLCON(3)); + /* set pll power up */ + writel(HIWORD_UPDATE(0, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + udelay(1); + /* wait for the pll to lock */ ret = rockchip_rk3399_pll_wait_lock(pll); if (ret) { -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2020-10-14 2:35 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-14 2:28 [PATCH v4 0/5] clk: rockchip: Support for some new features Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang 2020-10-14 2:28 ` [PATCH v4 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang 2020-10-14 2:28 ` [PATCH v4 2/5] clk: rockchip: fix up the frac clk get rate error Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang 2020-10-14 2:28 ` [PATCH v4 3/5] clk: rockchip: add a clock-type for muxes based in the pmugrf Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang [this message] 2020-10-14 2:28 ` [PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq Elaine Zhang 2020-10-14 2:28 ` [PATCH v4 5/5] clk: rockchip: support pll setting by auto Elaine Zhang 2020-10-14 2:28 ` Elaine Zhang -- strict thread matches above, loose matches on Subject: below -- 2019-12-04 8:18 [PATCH v4 0/5] clk: rockchip: Support for some new features Elaine Zhang 2019-12-04 8:18 ` [PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq Elaine Zhang 2019-12-30 19:06 ` Stephen Boyd 2019-12-30 19:06 ` Stephen Boyd 2019-12-30 19:06 ` Stephen Boyd
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