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From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	richard.henderson@linaro.org, qemu-devel@nongnu.org,
	space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
	kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH v4 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs
Date: Sat, 17 Oct 2020 10:11:52 +0300	[thread overview]
Message-ID: <20201017071154.20642-4-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20201017071154.20642-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
 target/riscv/cpu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d63031eb08..5916ebe5c2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -255,6 +255,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
     }
+    if (riscv_has_ext(env, RVJ)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte    ", env->mmte);
+        switch (env->priv) {
+        case PRV_U:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+                         env->upmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+                         env->upmmask);
+            break;
+        case PRV_S:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+                         env->spmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+                         env->spmmask);
+            break;
+        case PRV_M:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+                         env->mpmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+                         env->mpmmask);
+            break;
+        default:
+            assert(0 && "Unreachable");
+        }
+    }
 #endif
 
     for (i = 0; i < 32; i++) {
-- 
2.20.1



WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
	space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com,
	palmer@dabbelt.com, Alistair.Francis@wdc.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH v4 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs
Date: Sat, 17 Oct 2020 10:11:52 +0300	[thread overview]
Message-ID: <20201017071154.20642-4-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20201017071154.20642-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
 target/riscv/cpu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d63031eb08..5916ebe5c2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -255,6 +255,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
     }
+    if (riscv_has_ext(env, RVJ)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte    ", env->mmte);
+        switch (env->priv) {
+        case PRV_U:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+                         env->upmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+                         env->upmmask);
+            break;
+        case PRV_S:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+                         env->spmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+                         env->spmmask);
+            break;
+        case PRV_M:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+                         env->mpmbase);
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+                         env->mpmmask);
+            break;
+        default:
+            assert(0 && "Unreachable");
+        }
+    }
 #endif
 
     for (i = 0; i < 32; i++) {
-- 
2.20.1



  parent reply	other threads:[~2020-10-17  7:13 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-17  7:11 [PATCH v4 0/5] RISC-V Pointer Masking implementation Alexey Baturo
2020-10-17  7:11 ` Alexey Baturo
2020-10-17  7:11 ` [PATCH v4 1/5] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2020-10-17  7:11   ` Alexey Baturo
2020-10-21 20:22   ` Alistair Francis
2020-10-17  7:11 ` [PATCH v4 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Alexey Baturo
2020-10-17  7:11   ` Alexey Baturo
2020-10-17  7:11 ` Alexey Baturo [this message]
2020-10-17  7:11   ` [PATCH v4 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2020-10-17  7:11 ` [PATCH v4 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2020-10-17  7:11   ` Alexey Baturo
2020-10-17  7:11 ` [PATCH v4 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2020-10-17  7:11   ` Alexey Baturo

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