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From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S
Date: Wed, 21 Oct 2020 06:32:00 -0700	[thread overview]
Message-ID: <20201021133213.328994-6-aditya.swarup@intel.com> (raw)
In-Reply-To: <20201021133213.328994-1-aditya.swarup@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++--
 drivers/gpu/drm/i915/i915_reg.h              | 5 ++++-
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 60bacdbe7f92..70ca5d2e5b0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7333,6 +7333,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy <= PHY_E;
 	else if (IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_JSL_EHL(dev_priv))
@@ -7345,7 +7347,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv))
 		return false;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
@@ -7357,7 +7359,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+	if (IS_ALDERLAKE_S(i915) && port >= PORT_D)
+		return (enum phy)port - 2;
+	else if (IS_ROCKETLAKE(i915) && port >= PORT_D)
 		return (enum phy)port - 1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6b844ca7a9f..85c5e4fb3e7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1870,10 +1870,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
 #define _RKL_COMBOPHY_D			0x161000
+#define _ADL_COMBOPHY_E			0x16B000
+
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _EHL_COMBOPHY_C, \
-					      _RKL_COMBOPHY_D)
+					      _RKL_COMBOPHY_D, \
+					      _ADL_COMBOPHY_E)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.27.0

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  parent reply	other threads:[~2020-10-21 13:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-21 13:31 [Intel-gfx] [PATCH 00/18] Introduce Alderlake-S Aditya Swarup
2020-10-21 13:31 ` [Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2020-10-23 18:05   ` Matt Roper
2020-10-21 13:31 ` [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-10-21 20:43   ` Matt Roper
2020-10-21 20:57     ` Lucas De Marchi
2020-10-21 13:31 ` [Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-10-21 14:17   ` Jani Nikula
2020-10-21 13:31 ` [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-10-21 17:28   ` Lucas De Marchi
2020-10-22 23:26     ` Aditya Swarup
2020-10-23  0:40       ` Lucas De Marchi
2020-10-21 13:32 ` Aditya Swarup [this message]
2020-10-23 18:11   ` [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S Matt Roper
2020-10-21 13:32 ` [Intel-gfx] [PATCH 06/18] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2020-10-21 14:21   ` Jani Nikula
2020-10-21 13:32 ` [Intel-gfx] [PATCH 08/18] drm/i915/adl_s: Setup display outputs and HTI support " Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 09/18] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 10/18] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 11/18] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 12/18] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA Aditya Swarup
2020-11-04 10:38   ` Joonas Lahtinen
2020-11-04 14:07     ` Rodrigo Vivi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 14/18] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 15/18] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 16/18] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 17/18] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 18/18] drm/i915/adl_s: Load DMC Aditya Swarup
2020-10-21 14:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S Patchwork
2020-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-21 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-21 16:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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