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From: Biwen Li <biwen.li@oss.nxp.com>
To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
	leoyang.li@nxp.com, zhiqiang.hou@nxp.com, tglx@linutronix.de,
	jason@lakedaemon.net, maz@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	jiafei.pan@nxp.com, xiaobo.xie@nxp.com,
	linux-arm-kernel@lists.infradead.org, Biwen Li <biwen.li@nxp.com>
Subject: [PATCH 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
Date: Thu, 22 Oct 2020 16:44:10 +0800	[thread overview]
Message-ID: <20201022084410.28249-11-biwen.li@oss.nxp.com> (raw)
In-Reply-To: <20201022084410.28249-1-biwen.li@oss.nxp.com>

From: Biwen Li <biwen.li@nxp.com>

Update bindings for Layerscape external irqs,
support more SoCs(LS1043A, LS1046A, LS1088A,
LS208xA, LX216xA)

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 .../bindings/interrupt-controller/fsl,ls-extirq.txt         | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8cf..6c55eb25cf93 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
 * Freescale Layerscape external IRQs
 
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
 the polarity of certain external interrupt lines.
 
 The device node must be a child of the node representing the
@@ -8,6 +9,9 @@ Supplemental Configuration Unit (SCFG).
 
 Required properties:
 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+  "fsl,ls1043a-extirq": for LS1043A, LS1046A.
+  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
+
 - #interrupt-cells: Must be 2. The first element is the index of the
   external interrupt line. The second element is the trigger type.
 - #address-cells: Must be 0.
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Biwen Li <biwen.li@oss.nxp.com>
To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
	leoyang.li@nxp.com, zhiqiang.hou@nxp.com, tglx@linutronix.de,
	jason@lakedaemon.net, maz@kernel.org
Cc: Biwen Li <biwen.li@nxp.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	xiaobo.xie@nxp.com, jiafei.pan@nxp.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
Date: Thu, 22 Oct 2020 16:44:10 +0800	[thread overview]
Message-ID: <20201022084410.28249-11-biwen.li@oss.nxp.com> (raw)
In-Reply-To: <20201022084410.28249-1-biwen.li@oss.nxp.com>

From: Biwen Li <biwen.li@nxp.com>

Update bindings for Layerscape external irqs,
support more SoCs(LS1043A, LS1046A, LS1088A,
LS208xA, LX216xA)

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 .../bindings/interrupt-controller/fsl,ls-extirq.txt         | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8cf..6c55eb25cf93 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
 * Freescale Layerscape external IRQs
 
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
 the polarity of certain external interrupt lines.
 
 The device node must be a child of the node representing the
@@ -8,6 +9,9 @@ Supplemental Configuration Unit (SCFG).
 
 Required properties:
 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+  "fsl,ls1043a-extirq": for LS1043A, LS1046A.
+  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
+
 - #interrupt-cells: Must be 2. The first element is the index of the
   external interrupt line. The second element is the trigger type.
 - #address-cells: Must be 0.
-- 
2.17.1


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  parent reply	other threads:[~2020-10-22  8:53 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22  8:44 [PATCH 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt Biwen Li
2020-10-22  8:44 ` Biwen Li
2020-10-22  8:44 ` [PATCH 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 03/11] arm64: dts: ls1046a: " Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` [PATCH 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node Biwen Li
2020-10-22  8:44   ` Biwen Li
2020-10-22  8:44 ` Biwen Li [this message]
2020-10-22  8:44   ` [PATCH 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs Biwen Li

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