From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, uma.shankar@intel.com, seanpaul@chromium.org, Anshuman Gupta <anshuman.gupta@intel.com>, juston.li@intel.com Subject: [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Date: Thu, 22 Oct 2020 14:25:51 +0530 [thread overview] Message-ID: <20201022085552.18353-16-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201022085552.18353-1-anshuman.gupta@intel.com> Add support for HDCP 2.2 DP MST shim callback. This adds existing DP HDCP shim callback for Link Authentication and Encryption and HDCP 2.2 stream encryption callback. Cc: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- .../drm/i915/display/intel_display_types.h | 4 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 81 +++++++++++++++++-- 2 files changed, 77 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index dfb5be64e03a..4cbb151ff3cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -374,6 +374,10 @@ struct intel_hdcp_shim { int (*config_stream_type)(struct intel_digital_port *dig_port, bool is_repeater, u8 type); + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port, + bool enable); + /* HDCP2.2 Link Integrity Check */ int (*check_2_2_link)(struct intel_digital_port *dig_port, struct intel_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index a0c62e363c39..7e45b9964a29 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_strem_encryption(struct intel_digital_port *dig_port, return 0; } -static -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, - struct intel_connector *connector) +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port, + struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - struct intel_dp *intel_dp = &dig_port->dp; struct drm_dp_query_stream_enc_status_ack_reply reply; + struct intel_dp *intel_dp = &dig_port->dp; int ret; - if (!intel_dp_hdcp_check_link(dig_port, connector)) - return false; - ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr, connector->port, &reply); if (ret) { @@ -722,6 +718,70 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, return reply.auth_completed && reply.encryption_enabled; } +static +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + if (!intel_dp_hdcp_check_link(dig_port, connector)) + return false; + + return intel_dp_mst_get_qses_status(dig_port, connector); +} + +static int +intel_dp_mst_hdcp2_strem_encryption(struct intel_digital_port *dig_port, + bool enable) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *dp = &dig_port->dp; + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; + enum port port = dig_port->base.port; + /* HDCP2.x register uses stream transcoder */ + enum transcoder cpu_transcoder = hdcp->stream_transcoder; + int ret; + + if (enable && (intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) & + AUTH_STREAM_TYPE) != hdcp->content_type) { + drm_err(&i915->drm, "Seurity f/w didn't set correct auth strem_type\n"); + return -EINVAL; + } + + ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable); + if (ret) + return ret; + + /* Wait for encryption confirmation */ + if (intel_de_wait_for_register(i915, + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port), + STREAM_ENCRYPTION_STATUS, + enable ? STREAM_ENCRYPTION_STATUS : 0, + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n", + enable ? "enabled" : "disabled"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * DP v2.0 I.3.3 ignore the stream signature L' is QSES reply msg reply. + * I.3.5 MST source device may use a QSES msg to query downstream status + * for a particular stream. + */ +static +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + int ret; + + ret = intel_dp_hdcp2_check_link(dig_port, connector); + if (ret) + return ret; + + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL; +} + static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { .write_an_aksv = intel_dp_hdcp_write_an_aksv, .read_bksv = intel_dp_hdcp_read_bksv, @@ -735,7 +795,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { .stream_encryption = intel_dp_mst_hdcp_strem_encryption, .check_link = intel_dp_mst_hdcp_check_link, .hdcp_capable = intel_dp_hdcp_capable, - + .write_2_2_msg = intel_dp_hdcp2_write_msg, + .read_2_2_msg = intel_dp_hdcp2_read_msg, + .config_stream_type = intel_dp_hdcp2_config_stream_type, + .stream_2_2_encryption = intel_dp_mst_hdcp2_strem_encryption, + .check_2_2_link = intel_dp_mst_hdcp2_check_link, + .hdcp_2_2_capable = intel_dp_hdcp2_capable, .protocol = HDCP_PROTOCOL_DP, }; -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, seanpaul@chromium.org Subject: [Intel-gfx] [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Date: Thu, 22 Oct 2020 14:25:51 +0530 [thread overview] Message-ID: <20201022085552.18353-16-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201022085552.18353-1-anshuman.gupta@intel.com> Add support for HDCP 2.2 DP MST shim callback. This adds existing DP HDCP shim callback for Link Authentication and Encryption and HDCP 2.2 stream encryption callback. Cc: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- .../drm/i915/display/intel_display_types.h | 4 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 81 +++++++++++++++++-- 2 files changed, 77 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index dfb5be64e03a..4cbb151ff3cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -374,6 +374,10 @@ struct intel_hdcp_shim { int (*config_stream_type)(struct intel_digital_port *dig_port, bool is_repeater, u8 type); + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port, + bool enable); + /* HDCP2.2 Link Integrity Check */ int (*check_2_2_link)(struct intel_digital_port *dig_port, struct intel_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index a0c62e363c39..7e45b9964a29 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_strem_encryption(struct intel_digital_port *dig_port, return 0; } -static -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, - struct intel_connector *connector) +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port, + struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - struct intel_dp *intel_dp = &dig_port->dp; struct drm_dp_query_stream_enc_status_ack_reply reply; + struct intel_dp *intel_dp = &dig_port->dp; int ret; - if (!intel_dp_hdcp_check_link(dig_port, connector)) - return false; - ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr, connector->port, &reply); if (ret) { @@ -722,6 +718,70 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, return reply.auth_completed && reply.encryption_enabled; } +static +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + if (!intel_dp_hdcp_check_link(dig_port, connector)) + return false; + + return intel_dp_mst_get_qses_status(dig_port, connector); +} + +static int +intel_dp_mst_hdcp2_strem_encryption(struct intel_digital_port *dig_port, + bool enable) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *dp = &dig_port->dp; + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; + enum port port = dig_port->base.port; + /* HDCP2.x register uses stream transcoder */ + enum transcoder cpu_transcoder = hdcp->stream_transcoder; + int ret; + + if (enable && (intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) & + AUTH_STREAM_TYPE) != hdcp->content_type) { + drm_err(&i915->drm, "Seurity f/w didn't set correct auth strem_type\n"); + return -EINVAL; + } + + ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable); + if (ret) + return ret; + + /* Wait for encryption confirmation */ + if (intel_de_wait_for_register(i915, + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port), + STREAM_ENCRYPTION_STATUS, + enable ? STREAM_ENCRYPTION_STATUS : 0, + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n", + enable ? "enabled" : "disabled"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * DP v2.0 I.3.3 ignore the stream signature L' is QSES reply msg reply. + * I.3.5 MST source device may use a QSES msg to query downstream status + * for a particular stream. + */ +static +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + int ret; + + ret = intel_dp_hdcp2_check_link(dig_port, connector); + if (ret) + return ret; + + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL; +} + static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { .write_an_aksv = intel_dp_hdcp_write_an_aksv, .read_bksv = intel_dp_hdcp_read_bksv, @@ -735,7 +795,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { .stream_encryption = intel_dp_mst_hdcp_strem_encryption, .check_link = intel_dp_mst_hdcp_check_link, .hdcp_capable = intel_dp_hdcp_capable, - + .write_2_2_msg = intel_dp_hdcp2_write_msg, + .read_2_2_msg = intel_dp_hdcp2_read_msg, + .config_stream_type = intel_dp_hdcp2_config_stream_type, + .stream_2_2_encryption = intel_dp_mst_hdcp2_strem_encryption, + .check_2_2_link = intel_dp_mst_hdcp2_check_link, + .hdcp_2_2_capable = intel_dp_hdcp2_capable, .protocol = HDCP_PROTOCOL_DP, }; -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-22 9:36 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-22 8:55 [PATCH v3 00/16] HDCP 2.2 DP MST Support Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 04/16] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 11/16] drm/hdcp: Max MST content streams Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 12/16] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 13/16] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 8:55 ` Anshuman Gupta [this message] 2020-10-22 8:55 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta 2020-10-22 8:55 ` [PATCH v3 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta 2020-10-22 8:55 ` [Intel-gfx] " Anshuman Gupta 2020-10-22 11:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev5) Patchwork 2020-10-22 11:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-10-22 11:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-10-22 15:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-10-23 12:20 [PATCH v3 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta 2020-10-23 12:21 ` [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta 2020-10-27 7:20 ` Shankar, Uma
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