From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, daniel@ffwll.ch,
airlied@linux.ie, p.zabel@pengutronix.de,
chunkuang.hu@kernel.org, Fabien Parent <fparent@baylibre.com>
Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Fri, 23 Oct 2020 15:31:27 +0200 [thread overview]
Message-ID: <20201023133130.194140-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201023133130.194140-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, daniel@ffwll.ch, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, p.zabel@pengutronix.de,
matthias.bgg@gmail.com
Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Fri, 23 Oct 2020 15:31:27 +0200 [thread overview]
Message-ID: <20201023133130.194140-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201023133130.194140-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, daniel@ffwll.ch, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, p.zabel@pengutronix.de,
matthias.bgg@gmail.com
Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Fri, 23 Oct 2020 15:31:27 +0200 [thread overview]
Message-ID: <20201023133130.194140-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201023133130.194140-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, matthias.bgg@gmail.com
Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Fri, 23 Oct 2020 15:31:27 +0200 [thread overview]
Message-ID: <20201023133130.194140-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201023133130.194140-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-23 13:31 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 13:31 [PATCH v2 0/5] Add DRM/DSI support for MT8167 SoC Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` [PATCH v2 1/5] dt-bindings: display: mediatek: disp: add documentation " Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-30 15:49 ` Rob Herring
2020-10-30 15:49 ` Rob Herring
2020-10-30 15:49 ` Rob Herring
2020-10-30 15:49 ` Rob Herring
2020-11-08 1:53 ` Chun-Kuang Hu
2020-11-08 1:53 ` Chun-Kuang Hu
2020-11-08 1:53 ` Chun-Kuang Hu
2020-11-08 1:53 ` Chun-Kuang Hu
2020-10-23 13:31 ` Fabien Parent [this message]
2020-10-23 13:31 ` [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: " Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 15:49 ` Chun-Kuang Hu
2020-10-23 15:49 ` Chun-Kuang Hu
2020-10-23 15:49 ` Chun-Kuang Hu
2020-10-23 15:49 ` Chun-Kuang Hu
2021-08-09 14:06 ` Chun-Kuang Hu
2021-08-09 14:06 ` Chun-Kuang Hu
2021-08-09 14:06 ` Chun-Kuang Hu
2021-08-09 14:06 ` Chun-Kuang Hu
2020-10-23 13:31 ` [PATCH v2 3/5] drm/mediatek: add disp-color MT8167 support Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-11-08 1:54 ` Chun-Kuang Hu
2020-11-08 1:54 ` Chun-Kuang Hu
2020-11-08 1:54 ` Chun-Kuang Hu
2020-11-08 1:54 ` Chun-Kuang Hu
2020-10-23 13:31 ` [PATCH v2 4/5] drm/mediatek: add DDP support for MT8167 Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 15:45 ` Chun-Kuang Hu
2020-10-23 15:45 ` Chun-Kuang Hu
2020-10-23 15:45 ` Chun-Kuang Hu
2020-10-23 15:45 ` Chun-Kuang Hu
2020-11-08 1:55 ` Chun-Kuang Hu
2020-11-08 1:55 ` Chun-Kuang Hu
2020-11-08 1:55 ` Chun-Kuang Hu
2020-11-08 1:55 ` Chun-Kuang Hu
2020-10-23 13:31 ` [PATCH v2 5/5] drm/mediatek: Add support for main DDP path on MT8167 Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 13:31 ` Fabien Parent
2020-10-23 15:52 ` Chun-Kuang Hu
2020-10-23 15:52 ` Chun-Kuang Hu
2020-10-23 15:52 ` Chun-Kuang Hu
2020-10-23 15:52 ` Chun-Kuang Hu
2020-10-27 16:08 ` Fabien Parent
2020-10-27 16:08 ` Fabien Parent
2020-10-27 16:08 ` Fabien Parent
2020-10-27 16:08 ` Fabien Parent
2021-08-10 8:35 ` Matthias Brugger
2021-08-10 8:35 ` Matthias Brugger
2021-08-10 8:35 ` Matthias Brugger
2021-08-10 8:35 ` Matthias Brugger
2020-11-09 23:40 ` Chun-Kuang Hu
2020-11-09 23:40 ` Chun-Kuang Hu
2020-11-09 23:40 ` Chun-Kuang Hu
2020-11-09 23:40 ` Chun-Kuang Hu
2021-08-09 14:05 ` Chun-Kuang Hu
2021-08-09 14:05 ` Chun-Kuang Hu
2021-08-09 14:05 ` Chun-Kuang Hu
2021-08-09 14:05 ` Chun-Kuang Hu
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