From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 2/2] HAX: drm/i915: default to enable_guc=2
Date: Fri, 23 Oct 2020 15:22:47 -0700 [thread overview]
Message-ID: <20201023222247.5926-2-daniele.ceraolospurio@intel.com> (raw)
In-Reply-To: <20201023222247.5926-1-daniele.ceraolospurio@intel.com>
To enable GuC and HuC loading on all gen9+ CI machines.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 330c03e2b4f7..04b21c47d19f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -58,7 +58,7 @@ struct drm_printer;
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
- param(int, enable_guc, 0, 0400) \
+ param(int, enable_guc, 2, 0400) \
param(int, guc_log_level, -1, 0400) \
param(char *, guc_firmware_path, NULL, 0400) \
param(char *, huc_firmware_path, NULL, 0400) \
--
2.24.1
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next prev parent reply other threads:[~2020-10-23 22:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 22:22 [Intel-gfx] [CI 1/2] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Daniele Ceraolo Spurio
2020-10-23 22:22 ` Daniele Ceraolo Spurio [this message]
2020-10-23 23:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] " Patchwork
2020-10-27 23:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/guc: skip disabling CTBs before sanitizing the GuC (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-02-29 1:20 [Intel-gfx] [CI 1/2] drm/i915/huc: update TGL HuC to v7.0.12 Daniele Ceraolo Spurio
2020-02-29 1:20 ` [Intel-gfx] [CI 2/2] HAX: drm/i915: default to enable_guc=2 Daniele Ceraolo Spurio
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