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From: Biwen Li <biwen.li@oss.nxp.com>
To: linux@rasmusvillemoes.dk, shawnguo@kernel.org,
	robh+dt@kernel.org, mark.rutland@arm.com, leoyang.li@nxp.com,
	zhiqiang.hou@nxp.com, tglx@linutronix.de, jason@lakedaemon.net,
	maz@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	jiafei.pan@nxp.com, xiaobo.xie@nxp.com,
	linux-arm-kernel@lists.infradead.org, Biwen Li <biwen.li@nxp.com>
Subject: [v2 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
Date: Tue, 27 Oct 2020 12:46:19 +0800	[thread overview]
Message-ID: <20201027044619.41879-11-biwen.li@oss.nxp.com> (raw)
In-Reply-To: <20201027044619.41879-1-biwen.li@oss.nxp.com>

From: Biwen Li <biwen.li@nxp.com>

Update bindings for Layerscape external irqs,
support more SoCs(LS1043A, LS1046A, LS1088A,
LS208xA, LX216xA)

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v2:
	- update reg property
	- update compatible property

 .../bindings/interrupt-controller/fsl,ls-extirq.txt    | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8cf..0d635c24ef8b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
 * Freescale Layerscape external IRQs
 
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
 the polarity of certain external interrupt lines.
 
 The device node must be a child of the node representing the
@@ -8,12 +9,17 @@ Supplemental Configuration Unit (SCFG).
 
 Required properties:
 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+  "fsl,ls1043a-extirq": for LS1043A, LS1046A. SCFG_INTPCR[31:0] of these SoCs
+  is stored/read as SCFG_INTPCR[0:31] defaultly(bit reverse).
+  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
+
 - #interrupt-cells: Must be 2. The first element is the index of the
   external interrupt line. The second element is the trigger type.
 - #address-cells: Must be 0.
 - interrupt-controller: Identifies the node as an interrupt controller
 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
-  the SCFG.
+  the SCFG or the External Interrupt Control Register (IRQCR) in
+  the ISC.
 - interrupt-map: Specifies the mapping from external interrupts to GIC
   interrupts.
 - interrupt-map-mask: Must be <0xffffffff 0>.
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Biwen Li <biwen.li@oss.nxp.com>
To: linux@rasmusvillemoes.dk, shawnguo@kernel.org,
	robh+dt@kernel.org, mark.rutland@arm.com, leoyang.li@nxp.com,
	zhiqiang.hou@nxp.com, tglx@linutronix.de, jason@lakedaemon.net,
	maz@kernel.org
Cc: Biwen Li <biwen.li@nxp.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	xiaobo.xie@nxp.com, jiafei.pan@nxp.com,
	linux-arm-kernel@lists.infradead.org
Subject: [v2 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs
Date: Tue, 27 Oct 2020 12:46:19 +0800	[thread overview]
Message-ID: <20201027044619.41879-11-biwen.li@oss.nxp.com> (raw)
In-Reply-To: <20201027044619.41879-1-biwen.li@oss.nxp.com>

From: Biwen Li <biwen.li@nxp.com>

Update bindings for Layerscape external irqs,
support more SoCs(LS1043A, LS1046A, LS1088A,
LS208xA, LX216xA)

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v2:
	- update reg property
	- update compatible property

 .../bindings/interrupt-controller/fsl,ls-extirq.txt    | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8cf..0d635c24ef8b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
 * Freescale Layerscape external IRQs
 
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
 the polarity of certain external interrupt lines.
 
 The device node must be a child of the node representing the
@@ -8,12 +9,17 @@ Supplemental Configuration Unit (SCFG).
 
 Required properties:
 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+  "fsl,ls1043a-extirq": for LS1043A, LS1046A. SCFG_INTPCR[31:0] of these SoCs
+  is stored/read as SCFG_INTPCR[0:31] defaultly(bit reverse).
+  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
+
 - #interrupt-cells: Must be 2. The first element is the index of the
   external interrupt line. The second element is the trigger type.
 - #address-cells: Must be 0.
 - interrupt-controller: Identifies the node as an interrupt controller
 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
-  the SCFG.
+  the SCFG or the External Interrupt Control Register (IRQCR) in
+  the ISC.
 - interrupt-map: Specifies the mapping from external interrupts to GIC
   interrupts.
 - interrupt-map-mask: Must be <0xffffffff 0>.
-- 
2.17.1


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  parent reply	other threads:[~2020-10-27  4:56 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-27  4:46 [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt Biwen Li
2020-10-27  4:46 ` Biwen Li
2020-10-27  4:46 ` [v2 02/11] arm64: dts: ls1043a: add DT node for external interrupt lines Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 03/11] arm64: dts: ls1046a: " Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 04/11] arm64: dts: ls1046ardb: Add interrupt line for RTC node Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 05/11] arm64: dts: ls1088a: add DT node for external interrupt lines Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 06/11] arm64: dts: ls1088ardb: fix interrupt line for RTC node Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 08/11] arm64: dts: ls208xa-rdb: add interrupt line for RTC node Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 09/11] arm64: dts: lx2160a: add DT node for external interrupt lines Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` [v2 10/11] arm64: dts: lx2160ardb: fix interrupt line for RTC node Biwen Li
2020-10-27  4:46   ` Biwen Li
2020-10-27  4:46 ` Biwen Li [this message]
2020-10-27  4:46   ` [v2 11/11] dt-bindings: interrupt-controller: update bindings for supporting more SoCs Biwen Li
2020-10-27  7:40 ` [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt Rasmus Villemoes
2020-10-27  7:40   ` Rasmus Villemoes
2020-10-27  7:48   ` [EXT] " Biwen Li
2020-10-27  7:48     ` Biwen Li
2020-10-27 21:30     ` Leo Li
2020-10-27 21:30       ` Leo Li
2020-11-02  6:14       ` Biwen Li (OSS)
2020-11-02  6:14         ` Biwen Li (OSS)
2020-11-02 21:22         ` Leo Li
2020-11-02 21:22           ` Leo Li
2020-11-03  8:02           ` Rasmus Villemoes
2020-11-03  8:02             ` Rasmus Villemoes
2020-11-05 23:03             ` Leo Li
2020-11-05 23:03               ` Leo Li
2020-11-24  1:33               ` Li Yang
2020-11-24  1:33                 ` Li Yang
2020-11-30  1:38                 ` Biwen Li (OSS)
2020-11-30  1:38                   ` Biwen Li (OSS)
2020-10-27  9:33 ` Marc Zyngier
2020-10-27  9:33   ` Marc Zyngier
2020-10-27 10:35   ` Biwen Li (OSS)
2020-10-27 10:35     ` Biwen Li (OSS)
2020-10-27 10:43     ` Marc Zyngier
2020-10-27 10:43       ` Marc Zyngier
2020-10-27 10:55       ` Biwen Li (OSS)
2020-10-27 10:55         ` Biwen Li (OSS)

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