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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alistair Francis <alistair.francis@wdc.com>,
	Anup Patel <anup.patel@wdc.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	padmarao.begari@microchip.com,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Cyril.Jean@microchip.com
Subject: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
Date: Wed, 28 Oct 2020 16:27:59 -0700	[thread overview]
Message-ID: <20201028232759.1928479-4-atish.patra@wdc.com> (raw)
In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com>

Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/configs/defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d222d353d86d..2660fa05451e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,7 @@ CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_VIRT=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SMP=y
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
@@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_UAS=y
+CONFIG_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_MMC=y
 CONFIG_MMC_SPI=y
 CONFIG_RTC_CLASS=y
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	Cyril.Jean@microchip.com,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Anup Patel <anup.patel@wdc.com>,
	Atish Patra <atish.patra@wdc.com>,
	Rob Herring <robh+dt@kernel.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, padmarao.begari@microchip.com
Subject: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
Date: Wed, 28 Oct 2020 16:27:59 -0700	[thread overview]
Message-ID: <20201028232759.1928479-4-atish.patra@wdc.com> (raw)
In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com>

Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/configs/defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d222d353d86d..2660fa05451e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,7 @@ CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_VIRT=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SMP=y
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
@@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_UAS=y
+CONFIG_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_MMC=y
 CONFIG_MMC_SPI=y
 CONFIG_RTC_CLASS=y
-- 
2.25.1


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  parent reply	other threads:[~2020-10-28 23:28 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-28 23:27   ` Atish Patra
2020-10-30  9:08   ` Anup Patel
2020-10-30  9:08     ` Anup Patel
2020-11-03  9:55   ` Bin Meng
2020-11-03  9:55     ` Bin Meng
2020-11-06  7:14   ` Palmer Dabbelt
2020-11-06  7:14     ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-28 23:27   ` Atish Patra
2020-10-29 10:24   ` Ben Dooks
2020-10-29 10:24     ` Ben Dooks
2020-10-30  7:11     ` Atish Patra
2020-10-30  7:11       ` Atish Patra
2020-10-30 21:19       ` Ben Dooks
2020-10-30 21:19         ` Ben Dooks
2020-11-03 15:07         ` Atish Patra
2020-11-03 15:07           ` Atish Patra
2020-11-03 15:19           ` Ben Dooks
2020-11-03 15:19             ` Ben Dooks
2020-11-03 18:10           ` Cyril.Jean
2020-11-03 18:10             ` Cyril.Jean
2020-11-03 18:28             ` Ben Dooks
2020-11-03 18:28               ` Ben Dooks
2020-11-03 18:36               ` Atish Patra
2020-11-03 18:36                 ` Atish Patra
2020-11-03 18:39                 ` Ben Dooks
2020-11-03 18:39                   ` Ben Dooks
2020-11-03 18:45                   ` Atish Patra
2020-11-03 18:45                     ` Atish Patra
2020-11-03 18:40               ` Cyril.Jean
2020-11-03 18:40                 ` Cyril.Jean
2020-11-03 18:46                 ` Ben Dooks
2020-11-03 18:46                   ` Ben Dooks
2020-11-04  2:41     ` Bin Meng
2020-11-04  2:41       ` Bin Meng
2020-10-30  9:05   ` Anup Patel
2020-10-30  9:05     ` Anup Patel
2020-10-30 20:27     ` Atish Patra
2020-10-30 20:27       ` Atish Patra
2020-11-03 10:59       ` Ben Dooks
2020-11-03 10:59         ` Ben Dooks
2020-11-03 15:08         ` Atish Patra
2020-11-03 15:08           ` Atish Patra
2020-10-30 21:20     ` Ben Dooks
2020-10-30 21:20       ` Ben Dooks
2020-11-03 10:00     ` Bin Meng
2020-11-03 10:00       ` Bin Meng
2020-11-03 18:19       ` Cyril.Jean
2020-11-03 18:19         ` Cyril.Jean
2020-11-03 18:38         ` Atish Patra
2020-11-03 18:38           ` Atish Patra
2020-11-03 18:50           ` Cyril.Jean
2020-11-03 18:50             ` Cyril.Jean
2020-11-03 19:02             ` Atish Patra
2020-11-03 19:02               ` Atish Patra
2020-11-06  7:14   ` Palmer Dabbelt
2020-11-06  7:14     ` Palmer Dabbelt
2020-10-28 23:27 ` Atish Patra [this message]
2020-10-28 23:27   ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30  9:09   ` Anup Patel
2020-10-30  9:09     ` Anup Patel
2020-10-30 21:21     ` Ben Dooks
2020-10-30 21:21       ` Ben Dooks
2020-11-03 10:03   ` Bin Meng
2020-11-03 10:03     ` Bin Meng
2020-11-06  7:14   ` Palmer Dabbelt
2020-11-06  7:14     ` Palmer Dabbelt
2020-11-06  7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-11-06  7:14   ` Palmer Dabbelt
2020-11-06  7:37   ` Atish Patra
2020-11-06  7:37     ` Atish Patra
2020-11-06  8:11     ` Palmer Dabbelt
2020-11-06  8:11       ` Palmer Dabbelt

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