From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: hariom.pandey@intel.com
Subject: [Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
Date: Tue, 3 Nov 2020 19:16:51 +0530 [thread overview]
Message-ID: <20201103134651.165527-1-tejaskumarx.surendrakumar.upadhyay@intel.com> (raw)
As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.
Changes since V1:
- ehl_ used as to keep earliest platform prefix
- WA required B0 stepping onwards
Cc: Deak Imre <imre.deak@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..cb6ebf627c04 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
}
/*
- * Display WA #22010492432: tgl
+ * Display WA #22010492432: ehl, tgl
* Program half of the nominal DCO divider fraction value.
*/
static bool
-tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
- return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+ return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
+ IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) ||
+ IS_TIGERLAKE(i915)) &&
+ i915->dpll.ref_clks.nssc == 38400;
}
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2699,7 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+ if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3089,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
memset(pll_state, 0, sizeof(*pll_state));
- if (tgl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d548e10e1600..8bf59b57efc9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings kbl_revids[];
(IS_ICELAKE(p) && IS_REVID(p, since, until))
#define EHL_REVID_A0 0x0
+#define EHL_REVID_B0 0x2
#define IS_JSL_EHL_REVID(p, since, until) \
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
--
2.28.0
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next reply other threads:[~2020-11-03 13:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 13:46 Tejas Upadhyay [this message]
2020-11-03 14:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ehl: Implement W/A 22010492432 (rev2) Patchwork
2020-11-03 14:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-03 15:42 ` [Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432 Imre Deak
2020-11-03 16:31 ` Surendrakumar Upadhyay, TejaskumarX
2020-11-03 16:54 ` Imre Deak
2020-11-03 20:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Implement W/A 22010492432 (rev2) Patchwork
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