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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB
Date: Tue,  3 Nov 2020 07:21:32 -0800	[thread overview]
Message-ID: <20201103152150.2677566-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com>

From: Anup Patel <anup.patel@wdc.com>

Extend sifive_u machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
or Linux SiFive DTB to sifive_u machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201022053225.2596110-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b2472c6627..2f19a9cda2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -100,14 +100,25 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     int cpu;
     uint32_t *cells;
     char *nodename;
+    const char *dtb_filename;
     char ethclk_names[] = "pclk\0hclk";
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 
-    fdt = s->fdt = create_device_tree(&s->fdt_size);
-    if (!fdt) {
-        error_report("create_device_tree() failed");
-        exit(1);
+    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
+    if (dtb_filename) {
+        fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
+        if (!fdt) {
+            error_report("load_device_tree() failed");
+            exit(1);
+        }
+        goto update_bootargs;
+    } else {
+        fdt = s->fdt = create_device_tree(&s->fdt_size);
+        if (!fdt) {
+            error_report("create_device_tree() failed");
+            exit(1);
+        }
     }
 
     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
@@ -390,13 +401,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
-    if (cmdline) {
-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-    }
-
     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 
     g_free(nodename);
+
+update_bootargs:
+    if (cmdline) {
+        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+    }
 }
 
 static void sifive_u_machine_reset(void *opaque, int n, int level)
-- 
2.28.0



  reply	other threads:[~2020-11-03 15:41 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 15:21 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2020-11-03 15:21 ` Alistair Francis [this message]
2020-11-03 15:21 ` [PULL v2 02/19] hw/riscv: virt: Allow passing custom DTB Alistair Francis
2020-11-03 15:21 ` [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 15:21 ` [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-11-03 15:21 ` [PULL v2 05/19] target/riscv: Add PMP state description Alistair Francis
2020-11-03 15:21 ` [PULL v2 06/19] target/riscv: Add H extension " Alistair Francis
2020-11-03 15:21 ` [PULL v2 07/19] target/riscv: Add V " Alistair Francis
2020-11-03 15:21 ` [PULL v2 08/19] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-11-03 15:21 ` [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-11-03 15:21 ` [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-11-03 15:21 ` [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-11-03 15:21 ` [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-11-03 15:21 ` [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-11-03 15:21 ` [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-11-03 15:21 ` [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-11-03 15:21 ` [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-03 15:21 ` [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(' Alistair Francis
2020-11-03 21:07 ` [PULL v2 00/19] riscv-to-apply queue Peter Maydell

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