From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
Date: Thu, 5 Nov 2020 01:26:03 +0530 [thread overview]
Message-ID: <20201104195604.3334-2-uma.shankar@intel.com> (raw)
In-Reply-To: <20201104195604.3334-1-uma.shankar@intel.com>
There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..32c411414908 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ if (dev_priv->psr.sink_psr2_support &&
+ IS_TIGERLAKE(dev_priv)) {
+ fbc->no_fbc_reason = "not supported with PSR2";
+ return false;
+ }
+
if (!intel_fbc_can_enable(dev_priv))
return false;
--
2.26.2
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next prev parent reply other threads:[~2020-11-04 19:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 19:56 [Intel-gfx] [PATCH 0/2] Re-enable FBC on TGL Uma Shankar
2020-11-04 19:56 ` Uma Shankar [this message]
2020-11-05 6:42 ` [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Anshuman Gupta
2020-11-05 7:19 ` Shankar, Uma
2020-11-05 16:07 ` Souza, Jose
2020-11-05 16:27 ` Shankar, Uma
2020-11-05 17:38 ` Souza, Jose
2020-11-05 18:40 ` Shankar, Uma
2020-11-04 19:56 ` [Intel-gfx] [PATCH 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar
2020-11-04 21:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL Patchwork
2020-11-05 1:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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