From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: Chris Wilson <chris@chris-wilson.co.uk>, Mika Kuoppala <mika.kuoppala@linux.intel.com>, Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>, Akeem G Abodunrin <akeem.g.abodunrin@intel.com>, Balestrieri Francesco <francesco.balestrieri@intel.com>, Bloomfield Jon <jon.bloomfield@intel.com>, stable@vger.kernel.org Subject: [PATCH 03/22] drm/i915/gt: Limit VFE threads based on GT Date: Thu, 5 Nov 2020 10:11:15 +0000 [thread overview] Message-ID: <20201105101134.19716-3-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20201105101134.19716-1-chris@chris-wilson.co.uk> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the range [0, n-1] where n is #EU * (#threads/EU) with the number of threads based on plaform and the number of EU based on the number of slices and subslices. This is a fixed number per platform/gt, so appropriately limit the number of threads we spawn to match the device. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024 Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com> Cc: Bloomfield Jon <jon.bloomfield@intel.com> Cc: stable@vger.kernel.org # v5.7+ --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index d93d85cd3027..f3b8fea6226e 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -7,8 +7,6 @@ #include "i915_drv.h" #include "intel_gpu_commands.h" -#define MAX_URB_ENTRIES 64 -#define STATE_SIZE (4 * 1024) #define GT3_INLINE_DATA_DELAYS 0x1E00 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) @@ -34,8 +32,7 @@ struct batch_chunk { }; struct batch_vals { - u32 max_primitives; - u32 max_urb_entries; + u32 max_primitives; /* == number of VFE threads */ u32 cmd_size; u32 state_size; u32 state_start; @@ -50,18 +47,35 @@ static void batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) { if (IS_HASWELL(i915)) { - bv->max_primitives = 280; - bv->max_urb_entries = MAX_URB_ENTRIES; + switch (INTEL_INFO(i915)->gt) { + default: + case 1: + bv->max_primitives = 70; + break; + case 2: + bv->max_primitives = 140; + break; + case 3: + bv->max_primitives = 280; + break; + } bv->surface_height = 16 * 16; bv->surface_width = 32 * 2 * 16; } else { - bv->max_primitives = 128; - bv->max_urb_entries = MAX_URB_ENTRIES / 2; + switch (INTEL_INFO(i915)->gt) { + default: + case 1: /* including vlv */ + bv->max_primitives = 36; + break; + case 2: + bv->max_primitives = 128; + break; + } bv->surface_height = 16 * 8; bv->surface_width = 32 * 16; } bv->cmd_size = bv->max_primitives * 4096; - bv->state_size = STATE_SIZE; + bv->state_size = SZ_4K; bv->state_start = bv->cmd_size; bv->batch_size = bv->cmd_size + bv->state_size; bv->scratch_size = bv->surface_height * bv->surface_width; @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch, u32 urb_size, u32 curbe_size, u32 mode) { - u32 urb_entries = bv->max_urb_entries; u32 threads = bv->max_primitives - 1; u32 *cs = batch_alloc_items(batch, 32, 8); @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, *cs++ = 0; /* number of threads & urb entries for GPGPU vs Media Mode */ - *cs++ = threads << 16 | urb_entries << 8 | mode << 2; + *cs++ = threads << 16 | 1 << 8 | mode << 2; *cs++ = 0; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Chris Wilson <chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 03/22] drm/i915/gt: Limit VFE threads based on GT Date: Thu, 5 Nov 2020 10:11:15 +0000 [thread overview] Message-ID: <20201105101134.19716-3-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20201105101134.19716-1-chris@chris-wilson.co.uk> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the range [0, n-1] where n is #EU * (#threads/EU) with the number of threads based on plaform and the number of EU based on the number of slices and subslices. This is a fixed number per platform/gt, so appropriately limit the number of threads we spawn to match the device. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024 Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com> Cc: Bloomfield Jon <jon.bloomfield@intel.com> Cc: stable@vger.kernel.org # v5.7+ --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++++++++++++++------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index d93d85cd3027..f3b8fea6226e 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -7,8 +7,6 @@ #include "i915_drv.h" #include "intel_gpu_commands.h" -#define MAX_URB_ENTRIES 64 -#define STATE_SIZE (4 * 1024) #define GT3_INLINE_DATA_DELAYS 0x1E00 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) @@ -34,8 +32,7 @@ struct batch_chunk { }; struct batch_vals { - u32 max_primitives; - u32 max_urb_entries; + u32 max_primitives; /* == number of VFE threads */ u32 cmd_size; u32 state_size; u32 state_start; @@ -50,18 +47,35 @@ static void batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) { if (IS_HASWELL(i915)) { - bv->max_primitives = 280; - bv->max_urb_entries = MAX_URB_ENTRIES; + switch (INTEL_INFO(i915)->gt) { + default: + case 1: + bv->max_primitives = 70; + break; + case 2: + bv->max_primitives = 140; + break; + case 3: + bv->max_primitives = 280; + break; + } bv->surface_height = 16 * 16; bv->surface_width = 32 * 2 * 16; } else { - bv->max_primitives = 128; - bv->max_urb_entries = MAX_URB_ENTRIES / 2; + switch (INTEL_INFO(i915)->gt) { + default: + case 1: /* including vlv */ + bv->max_primitives = 36; + break; + case 2: + bv->max_primitives = 128; + break; + } bv->surface_height = 16 * 8; bv->surface_width = 32 * 16; } bv->cmd_size = bv->max_primitives * 4096; - bv->state_size = STATE_SIZE; + bv->state_size = SZ_4K; bv->state_start = bv->cmd_size; bv->batch_size = bv->cmd_size + bv->state_size; bv->scratch_size = bv->surface_height * bv->surface_width; @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch, u32 urb_size, u32 curbe_size, u32 mode) { - u32 urb_entries = bv->max_urb_entries; u32 threads = bv->max_primitives - 1; u32 *cs = batch_alloc_items(batch, 32, 8); @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, *cs++ = 0; /* number of threads & urb entries for GPGPU vs Media Mode */ - *cs++ = threads << 16 | urb_entries << 8 | mode << 2; + *cs++ = threads << 16 | 1 << 8 | mode << 2; *cs++ = 0; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-11-05 10:11 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-05 10:11 [Intel-gfx] [PATCH 01/22] drm/i915/gem: Allow backends to override pread implementation Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 02/22] drm/i915/gem: Pull phys pread/pwrite implementations to the backend Chris Wilson 2020-11-05 15:39 ` Matthew Auld 2020-11-05 15:40 ` Matthew Auld 2020-11-05 15:45 ` Chris Wilson 2020-11-05 16:02 ` Matthew Auld 2020-11-05 16:19 ` Chris Wilson 2020-11-05 10:11 ` Chris Wilson [this message] 2020-11-05 10:11 ` [Intel-gfx] [PATCH 03/22] drm/i915/gt: Limit VFE threads based on GT Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 04/22] drm/i915/gt: Ignore dt==0 for reporting underflows Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 05/22] drm/i915/gt: Defer enabling the breadcrumb interrupt to after submission Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 06/22] drm/i915/gt: Track signaled breadcrumbs outside of the breadcrumb spinlock Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 07/22] drm/i915/gt: Don't cancel the interrupt shadow too early Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 08/22] drm/i915/gt: Free stale request on destroying the virtual engine Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 09/22] drm/i915/gt: Protect context lifetime with RCU Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 10/22] drm/i915/gt: Split the breadcrumb spinlock between global and contexts Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 11/22] drm/i915/gt: Move the breadcrumb to the signaler if completed upon cancel Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 12/22] drm/i915/gt: Decouple completed requests on unwind Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 13/22] drm/i915/gt: Check for a completed last request once Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 14/22] drm/i915/gt: Replace direct submit with direct call to tasklet Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 15/22] drm/i915/gt: ce->inflight updates are now serialised Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 16/22] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 17/22] drm/i915/gt: Decouple inflight virtual engines Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 18/22] drm/i915/gt: Defer schedule_out until after the next dequeue Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 19/22] drm/i915/gt: Remove virtual breadcrumb before transfer Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 20/22] drm/i915/gt: Shrink the critical section for irq signaling Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 21/22] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson 2020-11-05 10:11 ` [Intel-gfx] [PATCH 22/22] drm/i915/gt: Simplify virtual engine handling for execlists_hold() Chris Wilson 2020-11-05 13:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/gem: Allow backends to override pread implementation Patchwork 2020-11-05 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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