From: Rob Herring <robh@kernel.org> To: unlisted-recipients:; (no To-header on input) Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I <kishon@ti.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, linux-omap@vger.kernel.org Subject: [PATCH v2 06/16] PCI: dwc/dra7xx: Use the common MSI irq_chip Date: Thu, 5 Nov 2020 15:11:49 -0600 [thread overview] Message-ID: <20201105211159.1814485-7-robh@kernel.org> (raw) In-Reply-To: <20201105211159.1814485-1-robh@kernel.org> The dra7xx MSI irq_chip implementation is identical to the default DWC one. The only difference is the interrupt handler as the MSI interrupt is muxed with other interrupts, but that doesn't affect the irq_chip part of it. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> --- drivers/pci/controller/dwc/pci-dra7xx.c | 125 ------------------------ 1 file changed, 125 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index a4aabc85dbb1..4d0c35a4aa59 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -377,133 +377,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) return 0; } -static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - u64 msi_target; - - msi_target = (u64)pp->msi_data; - - msg->address_lo = lower_32_bits(msi_target); - msg->address_hi = upper_32_bits(msi_target); - - msg->data = d->hwirq; - - dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", - (int)d->hwirq, msg->address_hi, msg->address_lo); -} - -static int dra7xx_pcie_msi_set_affinity(struct irq_data *d, - const struct cpumask *mask, - bool force) -{ - return -EINVAL; -} - -static void dra7xx_pcie_bottom_mask(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - pp->irq_mask[ctrl] |= BIT(bit); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, - pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); -} - -static void dra7xx_pcie_bottom_unmask(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - pp->irq_mask[ctrl] &= ~BIT(bit); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, - pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); -} - -static void dra7xx_pcie_bottom_ack(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); -} - -static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = { - .name = "DRA7XX-PCI-MSI", - .irq_ack = dra7xx_pcie_bottom_ack, - .irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg, - .irq_set_affinity = dra7xx_pcie_msi_set_affinity, - .irq_mask = dra7xx_pcie_bottom_mask, - .irq_unmask = dra7xx_pcie_bottom_unmask, -}; - -static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct device *dev = pci->dev; - u32 ctrl, num_ctrls; - int ret; - - pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - pp->irq_mask[ctrl] = ~0; - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - pp->irq_mask[ctrl]); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - ~0); - } - - ret = dw_pcie_allocate_domains(pp); - if (ret) - return ret; - - pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(dev, pp->msi_data); - if (ret) { - dev_err(dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - dw_pcie_free_msi(pp); - } - return ret; -} - static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { .host_init = dra7xx_pcie_host_init, - .msi_host_init = dra7xx_pcie_msi_host_init, }; static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, linux-pci@vger.kernel.org, Kishon Vijay Abraham I <kishon@ti.com>, Bjorn Helgaas <bhelgaas@google.com>, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/16] PCI: dwc/dra7xx: Use the common MSI irq_chip Date: Thu, 5 Nov 2020 15:11:49 -0600 [thread overview] Message-ID: <20201105211159.1814485-7-robh@kernel.org> (raw) In-Reply-To: <20201105211159.1814485-1-robh@kernel.org> The dra7xx MSI irq_chip implementation is identical to the default DWC one. The only difference is the interrupt handler as the MSI interrupt is muxed with other interrupts, but that doesn't affect the irq_chip part of it. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> --- drivers/pci/controller/dwc/pci-dra7xx.c | 125 ------------------------ 1 file changed, 125 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index a4aabc85dbb1..4d0c35a4aa59 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -377,133 +377,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) return 0; } -static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - u64 msi_target; - - msi_target = (u64)pp->msi_data; - - msg->address_lo = lower_32_bits(msi_target); - msg->address_hi = upper_32_bits(msi_target); - - msg->data = d->hwirq; - - dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", - (int)d->hwirq, msg->address_hi, msg->address_lo); -} - -static int dra7xx_pcie_msi_set_affinity(struct irq_data *d, - const struct cpumask *mask, - bool force) -{ - return -EINVAL; -} - -static void dra7xx_pcie_bottom_mask(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - pp->irq_mask[ctrl] |= BIT(bit); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, - pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); -} - -static void dra7xx_pcie_bottom_unmask(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - pp->irq_mask[ctrl] &= ~BIT(bit); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, - pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); -} - -static void dra7xx_pcie_bottom_ack(struct irq_data *d) -{ - struct pcie_port *pp = irq_data_get_irq_chip_data(d); - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - unsigned int res, bit, ctrl; - - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); -} - -static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = { - .name = "DRA7XX-PCI-MSI", - .irq_ack = dra7xx_pcie_bottom_ack, - .irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg, - .irq_set_affinity = dra7xx_pcie_msi_set_affinity, - .irq_mask = dra7xx_pcie_bottom_mask, - .irq_unmask = dra7xx_pcie_bottom_unmask, -}; - -static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct device *dev = pci->dev; - u32 ctrl, num_ctrls; - int ret; - - pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - pp->irq_mask[ctrl] = ~0; - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - pp->irq_mask[ctrl]); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - ~0); - } - - ret = dw_pcie_allocate_domains(pp); - if (ret) - return ret; - - pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(dev, pp->msi_data); - if (ret) { - dev_err(dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - dw_pcie_free_msi(pp); - } - return ret; -} - static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { .host_init = dra7xx_pcie_host_init, - .msi_host_init = dra7xx_pcie_msi_host_init, }; static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-05 21:12 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20201105211208eucas1p29087cdd73805e670aff9f3a43f644e05@eucas1p2.samsung.com> 2020-11-05 21:11 ` [PATCH v2 00/16] PCI: dwc: Another round of clean-ups Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 01/16] PCI: dwc: Support multiple ATU memory regions Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 02/16] PCI: dwc/intel-gw: Move ATU offset out of driver match data Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 03/16] PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 04/16] PCI: dwc/intel-gw: Remove some unneeded function wrappers Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 05/16] PCI: dwc: Ensure all outbound ATU windows are reset Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring [this message] 2020-11-05 21:11 ` [PATCH v2 06/16] PCI: dwc/dra7xx: Use the common MSI irq_chip Rob Herring 2020-11-05 21:11 ` [PATCH v2 07/16] PCI: dwc: Drop the .set_num_vectors() host op Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 08/16] PCI: dwc: Move MSI interrupt setup into DWC common code Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 09/16] PCI: dwc: Rework MSI initialization Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-09 2:53 ` Jisheng Zhang 2020-11-09 2:53 ` Jisheng Zhang 2020-11-09 2:53 ` Jisheng Zhang 2020-11-05 21:11 ` [PATCH v2 10/16] PCI: dwc: Move link handling into common code Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 11/16] PCI: dwc: Move dw_pcie_msi_init() into core Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 12/16] PCI: dwc: Move dw_pcie_setup_rc() to DWC common code Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 13/16] PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init() Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 14/16] Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'" Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 15/16] PCI: dwc: Move inbound and outbound windows to common struct Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-05 21:11 ` [PATCH v2 16/16] PCI: dwc: Detect number of iATU windows Rob Herring 2020-11-05 21:11 ` Rob Herring 2020-11-06 9:17 ` [PATCH v2 00/16] PCI: dwc: Another round of clean-ups Marek Szyprowski 2020-11-06 9:17 ` Marek Szyprowski 2020-11-06 9:17 ` Marek Szyprowski 2020-11-06 9:17 ` Marek Szyprowski 2020-11-19 11:01 ` Lorenzo Pieralisi 2020-11-19 11:01 ` Lorenzo Pieralisi 2020-11-19 11:01 ` Lorenzo Pieralisi 2020-11-19 11:01 ` Lorenzo Pieralisi
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