From: Leo Yan <leo.yan@linaro.org> To: Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com>, Ian Rogers <irogers@google.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Namhyung Kim <namhyung@kernel.org>, John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Andi Kleen <ak@linux.intel.com>, Kemeng Shi <shikemeng@huawei.com>, Sergey Senozhatsky <sergey.senozhatsky@gmail.com>, Al Grant <Al.Grant@arm.com>, James Clark <james.clark@arm.com>, Wei Li <liwei391@huawei.com>, Andre Przywara <andre.przywara@arm.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan <leo.yan@linaro.org> Subject: [PATCH v4 6/9] perf auxtrace: Add itrace option '-M' for memory events Date: Fri, 6 Nov 2020 17:48:50 +0800 [thread overview] Message-ID: <20201106094853.21082-7-leo.yan@linaro.org> (raw) In-Reply-To: <20201106094853.21082-1-leo.yan@linaro.org> This patch is to add itrace option '-M' to synthesize memory event. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- tools/perf/Documentation/itrace.txt | 1 + tools/perf/util/auxtrace.c | 4 ++++ tools/perf/util/auxtrace.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation/itrace.txt index d3740c8f399b..079cdfabb352 100644 --- a/tools/perf/Documentation/itrace.txt +++ b/tools/perf/Documentation/itrace.txt @@ -11,6 +11,7 @@ d create a debug log f synthesize first level cache events m synthesize last level cache events + M synthesize memory events t synthesize TLB events a synthesize remote access events g synthesize a call chain (use with i or x) diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 42a85c86421d..62e7f6c5f8b5 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1333,6 +1333,7 @@ void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, synth_opts->flc = true; synth_opts->llc = true; synth_opts->tlb = true; + synth_opts->mem = true; synth_opts->remote_access = true; if (no_sample) { @@ -1554,6 +1555,9 @@ int itrace_parse_synth_opts(const struct option *opt, const char *str, case 'a': synth_opts->remote_access = true; break; + case 'M': + synth_opts->mem = true; + break; case 'q': synth_opts->quick += 1; break; diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index 951d2d14cf24..7e5c9e1552bd 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -88,6 +88,7 @@ enum itrace_period_type { * @llc: whether to synthesize last level cache events * @tlb: whether to synthesize TLB events * @remote_access: whether to synthesize remote access events + * @mem: whether to synthesize memory events * @callchain_sz: maximum callchain size * @last_branch_sz: branch context size * @period: 'instructions' events period @@ -126,6 +127,7 @@ struct itrace_synth_opts { bool llc; bool tlb; bool remote_access; + bool mem; unsigned int callchain_sz; unsigned int last_branch_sz; unsigned long long period; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Leo Yan <leo.yan@linaro.org> To: Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com>, Ian Rogers <irogers@google.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Namhyung Kim <namhyung@kernel.org>, John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Andi Kleen <ak@linux.intel.com>, Kemeng Shi <shikemeng@huawei.com>, Sergey Senozhatsky <sergey.senozhatsky@gmail.com>, Al Grant <Al.Grant@arm.com>, James Clark <james.clark@arm.com>, Wei Li <liwei391@huawei.com>, Andre Przywara <andre.przywara@arm.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan <leo.yan@linaro.org> Subject: [PATCH v4 6/9] perf auxtrace: Add itrace option '-M' for memory events Date: Fri, 6 Nov 2020 17:48:50 +0800 [thread overview] Message-ID: <20201106094853.21082-7-leo.yan@linaro.org> (raw) In-Reply-To: <20201106094853.21082-1-leo.yan@linaro.org> This patch is to add itrace option '-M' to synthesize memory event. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- tools/perf/Documentation/itrace.txt | 1 + tools/perf/util/auxtrace.c | 4 ++++ tools/perf/util/auxtrace.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation/itrace.txt index d3740c8f399b..079cdfabb352 100644 --- a/tools/perf/Documentation/itrace.txt +++ b/tools/perf/Documentation/itrace.txt @@ -11,6 +11,7 @@ d create a debug log f synthesize first level cache events m synthesize last level cache events + M synthesize memory events t synthesize TLB events a synthesize remote access events g synthesize a call chain (use with i or x) diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 42a85c86421d..62e7f6c5f8b5 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1333,6 +1333,7 @@ void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, synth_opts->flc = true; synth_opts->llc = true; synth_opts->tlb = true; + synth_opts->mem = true; synth_opts->remote_access = true; if (no_sample) { @@ -1554,6 +1555,9 @@ int itrace_parse_synth_opts(const struct option *opt, const char *str, case 'a': synth_opts->remote_access = true; break; + case 'M': + synth_opts->mem = true; + break; case 'q': synth_opts->quick += 1; break; diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index 951d2d14cf24..7e5c9e1552bd 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -88,6 +88,7 @@ enum itrace_period_type { * @llc: whether to synthesize last level cache events * @tlb: whether to synthesize TLB events * @remote_access: whether to synthesize remote access events + * @mem: whether to synthesize memory events * @callchain_sz: maximum callchain size * @last_branch_sz: branch context size * @period: 'instructions' events period @@ -126,6 +127,7 @@ struct itrace_synth_opts { bool llc; bool tlb; bool remote_access; + bool mem; unsigned int callchain_sz; unsigned int last_branch_sz; unsigned long long period; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-06 9:49 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-06 9:48 [PATCH v4 0/9] perf mem/c2c: Support AUX trace Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 1/9] perf mem: Search event name with more flexible path Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 2/9] perf mem: Introduce weak function perf_mem_events__ptr() Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 3/9] perf mem: Support new memory event PERF_MEM_EVENTS__LOAD_STORE Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 4/9] perf c2c: Support " Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 5/9] perf mem: Only initialize memory event for recording Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` Leo Yan [this message] 2020-11-06 9:48 ` [PATCH v4 6/9] perf auxtrace: Add itrace option '-M' for memory events Leo Yan 2020-11-06 9:48 ` [PATCH v4 7/9] perf mem: Support AUX trace Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 8/9] perf c2c: " Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-06 9:48 ` [PATCH v4 9/9] perf mem: Support Arm SPE events Leo Yan 2020-11-06 9:48 ` Leo Yan 2020-11-11 12:35 ` [PATCH v4 0/9] perf mem/c2c: Support AUX trace Jiri Olsa 2020-11-11 12:35 ` Jiri Olsa
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