From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org, linux-kernel@vger.kernel.org, anshuman.khandual@arm.com, jonathan.zhouwen@huawei.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Date: Thu, 19 Nov 2020 16:45:34 +0000 [thread overview] Message-ID: <20201119164547.2982871-13-suzuki.poulose@arm.com> (raw) In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com> The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 6f776f075602..85a165d1245e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -130,6 +130,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -169,8 +184,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4_os_unlock(drvdata); rc = coresight_claim_device_unlocked(csdev); @@ -271,7 +285,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -528,7 +542,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); if (!drvdata->skip_power_up) { /* power can be removed from the trace unit now */ @@ -569,8 +583,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -680,8 +693,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -846,7 +858,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1227,8 +1239,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1341,7 +1352,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1352,8 +1363,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1438,7 +1448,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>, linux-kernel@vger.kernel.org, jonathan.zhouwen@huawei.com, mike.leach@linaro.org Subject: [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Date: Thu, 19 Nov 2020 16:45:34 +0000 [thread overview] Message-ID: <20201119164547.2982871-13-suzuki.poulose@arm.com> (raw) In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com> The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 6f776f075602..85a165d1245e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -130,6 +130,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -169,8 +184,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4_os_unlock(drvdata); rc = coresight_claim_device_unlocked(csdev); @@ -271,7 +285,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -528,7 +542,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); if (!drvdata->skip_power_up) { /* power can be removed from the trace unit now */ @@ -569,8 +583,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -680,8 +693,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -846,7 +858,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1227,8 +1239,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1341,7 +1352,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1352,8 +1363,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1438,7 +1448,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-19 16:46 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-19 16:45 [PATCH v4 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-20 5:40 ` Sai Prakash Ranjan 2020-11-27 18:55 ` Mathieu Poirier 2020-11-27 18:55 ` Mathieu Poirier 2020-11-30 9:37 ` Suzuki K Poulose 2020-11-30 9:37 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 03/25] coresight: Introduce device access abstraction Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-27 19:11 ` Mathieu Poirier 2020-11-27 19:11 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 20:55 ` Mathieu Poirier 2020-11-30 20:55 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:04 ` Mathieu Poirier 2020-11-30 21:04 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:19 ` Mathieu Poirier 2020-11-30 21:19 ` Mathieu Poirier 2020-11-19 16:45 ` Suzuki K Poulose [this message] 2020-11-19 16:45 ` [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:25 ` Mathieu Poirier 2020-11-30 21:25 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 14/25] coresight: etm4x: Clean up " Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:45 ` Mathieu Poirier 2020-11-30 21:45 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:48 ` Mathieu Poirier 2020-11-30 21:48 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 21:53 ` Mathieu Poirier 2020-11-30 21:53 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-27 18:28 ` Mathieu Poirier 2020-11-27 18:28 ` Mathieu Poirier 2020-11-30 9:30 ` Suzuki K Poulose 2020-11-30 9:30 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-30 22:42 ` Mathieu Poirier 2020-11-30 22:42 ` Mathieu Poirier 2020-11-19 16:45 ` [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-23 7:58 ` Tingwei Zhang 2020-11-23 9:39 ` Suzuki K Poulose 2020-11-23 9:39 ` Suzuki K Poulose 2020-11-24 0:41 ` Tingwei Zhang 2020-11-24 11:38 ` Suzuki K Poulose 2020-11-24 11:38 ` Suzuki K Poulose 2020-11-25 4:57 ` Tingwei Zhang 2020-11-19 16:45 ` [PATCH v4 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 17:18 ` Catalin Marinas 2020-11-19 17:18 ` Catalin Marinas 2020-11-20 10:03 ` Suzuki K Poulose 2020-11-20 10:03 ` Suzuki K Poulose 2020-11-19 16:45 ` [PATCH v4 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose 2020-11-19 16:45 ` Suzuki K Poulose 2020-11-19 17:22 ` Catalin Marinas 2020-11-19 17:22 ` Catalin Marinas 2020-11-20 10:03 ` Suzuki K Poulose 2020-11-20 10:03 ` Suzuki K Poulose
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