From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org,
linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
jonathan.zhouwen@huawei.com, coresight@lists.linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access
Date: Thu, 19 Nov 2020 16:45:41 +0000 [thread overview]
Message-ID: <20201119164547.2982871-20-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com>
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index f1908e6f2180..7ac0a185c146 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -187,6 +187,15 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
/* Disable the trace unit before programming trace registers */
etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
+ /*
+ * If we use system instructions, we need to synchronize the
+ * write to the TRCPRGCTLR, before accessing the TRCSTATR.
+ * See ARM IHI0064F, section
+ * "4.3.7 Synchronization of register updates"
+ */
+ if (!csa->io_mem)
+ isb();
+
/* wait for TRCSTATR.IDLE to go up */
if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
dev_err(etm_dev,
@@ -265,6 +274,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
/* Enable the trace unit */
etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
+ /* Synchronize the register updates for sysreg access */
+ if (!csa->io_mem)
+ isb();
+
/* wait for TRCSTATR.IDLE to go back down to '0' */
if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
dev_err(etm_dev,
--
2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com,
coresight@lists.linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-kernel@vger.kernel.org, jonathan.zhouwen@huawei.com,
mike.leach@linaro.org
Subject: [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access
Date: Thu, 19 Nov 2020 16:45:41 +0000 [thread overview]
Message-ID: <20201119164547.2982871-20-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com>
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index f1908e6f2180..7ac0a185c146 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -187,6 +187,15 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
/* Disable the trace unit before programming trace registers */
etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
+ /*
+ * If we use system instructions, we need to synchronize the
+ * write to the TRCPRGCTLR, before accessing the TRCSTATR.
+ * See ARM IHI0064F, section
+ * "4.3.7 Synchronization of register updates"
+ */
+ if (!csa->io_mem)
+ isb();
+
/* wait for TRCSTATR.IDLE to go up */
if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
dev_err(etm_dev,
@@ -265,6 +274,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
/* Enable the trace unit */
etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
+ /* Synchronize the register updates for sysreg access */
+ if (!csa->io_mem)
+ isb();
+
/* wait for TRCSTATR.IDLE to go back down to '0' */
if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
dev_err(etm_dev,
--
2.24.1
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next prev parent reply other threads:[~2020-11-19 16:46 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 16:45 [PATCH v4 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-20 5:40 ` Sai Prakash Ranjan
2020-11-27 18:55 ` Mathieu Poirier
2020-11-27 18:55 ` Mathieu Poirier
2020-11-30 9:37 ` Suzuki K Poulose
2020-11-30 9:37 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-27 19:11 ` Mathieu Poirier
2020-11-27 19:11 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 20:55 ` Mathieu Poirier
2020-11-30 20:55 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:04 ` Mathieu Poirier
2020-11-30 21:04 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:19 ` Mathieu Poirier
2020-11-30 21:19 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:25 ` Mathieu Poirier
2020-11-30 21:25 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:45 ` Mathieu Poirier
2020-11-30 21:45 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:48 ` Mathieu Poirier
2020-11-30 21:48 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:53 ` Mathieu Poirier
2020-11-30 21:53 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-27 18:28 ` Mathieu Poirier
2020-11-27 18:28 ` Mathieu Poirier
2020-11-30 9:30 ` Suzuki K Poulose
2020-11-30 9:30 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 22:42 ` Mathieu Poirier
2020-11-30 22:42 ` Mathieu Poirier
2020-11-19 16:45 ` Suzuki K Poulose [this message]
2020-11-19 16:45 ` [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-23 7:58 ` Tingwei Zhang
2020-11-23 9:39 ` Suzuki K Poulose
2020-11-23 9:39 ` Suzuki K Poulose
2020-11-24 0:41 ` Tingwei Zhang
2020-11-24 11:38 ` Suzuki K Poulose
2020-11-24 11:38 ` Suzuki K Poulose
2020-11-25 4:57 ` Tingwei Zhang
2020-11-19 16:45 ` [PATCH v4 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 17:18 ` Catalin Marinas
2020-11-19 17:18 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 17:22 ` Catalin Marinas
2020-11-19 17:22 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-20 10:03 ` Suzuki K Poulose
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