From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org,
linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
jonathan.zhouwen@huawei.com, coresight@lists.linaro.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions
Date: Thu, 19 Nov 2020 16:45:46 +0000 [thread overview]
Message-ID: <20201119164547.2982871-25-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com>
From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ split the register definitions to separate patch
rename some of the symbols ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/sysreg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d52c1b3ce589..8bfca08ea839 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -187,6 +187,7 @@
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
@@ -462,6 +463,7 @@
#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
@@ -814,6 +816,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
@@ -988,6 +991,14 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
+#define TRFCR_ELx_TS_SHIFT 5
+#define TRFCR_ELx_TS_VIRTUAL ((0x1) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL ((0x3) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX BIT(3)
+#define TRFCR_ELx_ExTRE BIT(1)
+#define TRFCR_ELx_E0TRE BIT(0)
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
--
2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com,
Catalin Marinas <catalin.marinas@arm.com>,
coresight@lists.linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>,
jonathan.zhouwen@huawei.com, mike.leach@linaro.org
Subject: [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions
Date: Thu, 19 Nov 2020 16:45:46 +0000 [thread overview]
Message-ID: <20201119164547.2982871-25-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201119164547.2982871-1-suzuki.poulose@arm.com>
From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ split the register definitions to separate patch
rename some of the symbols ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/sysreg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d52c1b3ce589..8bfca08ea839 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -187,6 +187,7 @@
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
@@ -462,6 +463,7 @@
#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
@@ -814,6 +816,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
@@ -988,6 +991,14 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
+#define TRFCR_ELx_TS_SHIFT 5
+#define TRFCR_ELx_TS_VIRTUAL ((0x1) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL ((0x3) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX BIT(3)
+#define TRFCR_ELx_ExTRE BIT(1)
+#define TRFCR_ELx_E0TRE BIT(0)
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
--
2.24.1
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next prev parent reply other threads:[~2020-11-19 16:46 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 16:45 [PATCH v4 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-20 5:40 ` Sai Prakash Ranjan
2020-11-27 18:55 ` Mathieu Poirier
2020-11-27 18:55 ` Mathieu Poirier
2020-11-30 9:37 ` Suzuki K Poulose
2020-11-30 9:37 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-27 19:11 ` Mathieu Poirier
2020-11-27 19:11 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 20:55 ` Mathieu Poirier
2020-11-30 20:55 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:04 ` Mathieu Poirier
2020-11-30 21:04 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:19 ` Mathieu Poirier
2020-11-30 21:19 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:25 ` Mathieu Poirier
2020-11-30 21:25 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:45 ` Mathieu Poirier
2020-11-30 21:45 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:48 ` Mathieu Poirier
2020-11-30 21:48 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 21:53 ` Mathieu Poirier
2020-11-30 21:53 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-27 18:28 ` Mathieu Poirier
2020-11-27 18:28 ` Mathieu Poirier
2020-11-30 9:30 ` Suzuki K Poulose
2020-11-30 9:30 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-30 22:42 ` Mathieu Poirier
2020-11-30 22:42 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-23 7:58 ` Tingwei Zhang
2020-11-23 9:39 ` Suzuki K Poulose
2020-11-23 9:39 ` Suzuki K Poulose
2020-11-24 0:41 ` Tingwei Zhang
2020-11-24 11:38 ` Suzuki K Poulose
2020-11-24 11:38 ` Suzuki K Poulose
2020-11-25 4:57 ` Tingwei Zhang
2020-11-19 16:45 ` [PATCH v4 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose [this message]
2020-11-19 16:45 ` [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-11-19 17:18 ` Catalin Marinas
2020-11-19 17:18 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2020-11-19 16:45 ` Suzuki K Poulose
2020-11-19 17:22 ` Catalin Marinas
2020-11-19 17:22 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-20 10:03 ` Suzuki K Poulose
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