All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>,
	Viresh Kumar <vireshk@kernel.org>,
	Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH v10 02/19] memory: tegra20: Support hardware versioning and clean up OPP table initialization
Date: Mon, 23 Nov 2020 03:27:06 +0300	[thread overview]
Message-ID: <20201123002723.28463-3-digetx@gmail.com> (raw)
In-Reply-To: <20201123002723.28463-1-digetx@gmail.com>

Support hardware versioning, which is now required for Tegra20 EMC OPP.
Clean up OPP table initialization by using a error code returned by OPP
API for judging about the OPP table presence in a device-tree and remove
OPP regulator initialization because we're now going to use power domain
instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par
with the Tegra30/124 EMC drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/tegra20-emc.c | 48 +++++++++++++-----------------
 1 file changed, 20 insertions(+), 28 deletions(-)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 0320d9df4a20..686aaf477d8a 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -910,43 +910,36 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc)
 
 static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 {
-	struct opp_table *reg_opp_table = NULL, *clk_opp_table;
-	const char *rname = "core";
+	u32 hw_version = BIT(tegra_sku_info.soc_process_id);
+	struct opp_table *clk_opp_table, *hw_opp_table;
 	int err;
 
-	/*
-	 * Legacy device-trees don't have OPP table and EMC driver isn't
-	 * useful in this case.
-	 */
-	if (!device_property_present(emc->dev, "operating-points-v2")) {
-		dev_err(emc->dev,
-			"OPP table not found, please update your device tree\n");
-		return -ENODEV;
-	}
-
-	/* voltage scaling is optional */
-	if (device_property_present(emc->dev, "core-supply")) {
-		reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1);
-		if (IS_ERR(reg_opp_table))
-			return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table),
-					     "failed to set OPP regulator\n");
-	}
-
 	clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL);
 	err = PTR_ERR_OR_ZERO(clk_opp_table);
 	if (err) {
 		dev_err(emc->dev, "failed to set OPP clk: %d\n", err);
-		goto put_reg_table;
+		return err;
 	}
 
-	err = dev_pm_opp_of_add_table(emc->dev);
+	hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
+	err = PTR_ERR_OR_ZERO(hw_opp_table);
 	if (err) {
-		dev_err(emc->dev, "failed to add OPP table: %d\n", err);
+		dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
 		goto put_clk_table;
 	}
 
-	dev_info(emc->dev, "current clock rate %lu MHz\n",
-		 clk_get_rate(emc->clk) / 1000000);
+	err = dev_pm_opp_of_add_table(emc->dev);
+	if (err) {
+		if (err == -ENODEV)
+			dev_err(emc->dev, "OPP table not found, please update your device tree\n");
+		else
+			dev_err(emc->dev, "failed to add OPP table: %d\n", err);
+
+		goto put_hw_table;
+	}
+
+	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+		 hw_version, clk_get_rate(emc->clk) / 1000000);
 
 	/* first dummy rate-set initializes voltage state */
 	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
@@ -959,11 +952,10 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 
 remove_table:
 	dev_pm_opp_of_remove_table(emc->dev);
+put_hw_table:
+	dev_pm_opp_put_supported_hw(hw_opp_table);
 put_clk_table:
 	dev_pm_opp_put_clkname(clk_opp_table);
-put_reg_table:
-	if (reg_opp_table)
-		dev_pm_opp_put_regulators(reg_opp_table);
 
 	return err;
 }
-- 
2.29.2


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Mikko Perttunen <cyndis@kapsi.fi>,
	Viresh Kumar <vireshk@kernel.org>,
	Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org
Subject: [PATCH v10 02/19] memory: tegra20: Support hardware versioning and clean up OPP table initialization
Date: Mon, 23 Nov 2020 03:27:06 +0300	[thread overview]
Message-ID: <20201123002723.28463-3-digetx@gmail.com> (raw)
In-Reply-To: <20201123002723.28463-1-digetx@gmail.com>

Support hardware versioning, which is now required for Tegra20 EMC OPP.
Clean up OPP table initialization by using a error code returned by OPP
API for judging about the OPP table presence in a device-tree and remove
OPP regulator initialization because we're now going to use power domain
instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par
with the Tegra30/124 EMC drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/tegra20-emc.c | 48 +++++++++++++-----------------
 1 file changed, 20 insertions(+), 28 deletions(-)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 0320d9df4a20..686aaf477d8a 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -910,43 +910,36 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc)
 
 static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 {
-	struct opp_table *reg_opp_table = NULL, *clk_opp_table;
-	const char *rname = "core";
+	u32 hw_version = BIT(tegra_sku_info.soc_process_id);
+	struct opp_table *clk_opp_table, *hw_opp_table;
 	int err;
 
-	/*
-	 * Legacy device-trees don't have OPP table and EMC driver isn't
-	 * useful in this case.
-	 */
-	if (!device_property_present(emc->dev, "operating-points-v2")) {
-		dev_err(emc->dev,
-			"OPP table not found, please update your device tree\n");
-		return -ENODEV;
-	}
-
-	/* voltage scaling is optional */
-	if (device_property_present(emc->dev, "core-supply")) {
-		reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1);
-		if (IS_ERR(reg_opp_table))
-			return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table),
-					     "failed to set OPP regulator\n");
-	}
-
 	clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL);
 	err = PTR_ERR_OR_ZERO(clk_opp_table);
 	if (err) {
 		dev_err(emc->dev, "failed to set OPP clk: %d\n", err);
-		goto put_reg_table;
+		return err;
 	}
 
-	err = dev_pm_opp_of_add_table(emc->dev);
+	hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
+	err = PTR_ERR_OR_ZERO(hw_opp_table);
 	if (err) {
-		dev_err(emc->dev, "failed to add OPP table: %d\n", err);
+		dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
 		goto put_clk_table;
 	}
 
-	dev_info(emc->dev, "current clock rate %lu MHz\n",
-		 clk_get_rate(emc->clk) / 1000000);
+	err = dev_pm_opp_of_add_table(emc->dev);
+	if (err) {
+		if (err == -ENODEV)
+			dev_err(emc->dev, "OPP table not found, please update your device tree\n");
+		else
+			dev_err(emc->dev, "failed to add OPP table: %d\n", err);
+
+		goto put_hw_table;
+	}
+
+	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+		 hw_version, clk_get_rate(emc->clk) / 1000000);
 
 	/* first dummy rate-set initializes voltage state */
 	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
@@ -959,11 +952,10 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 
 remove_table:
 	dev_pm_opp_of_remove_table(emc->dev);
+put_hw_table:
+	dev_pm_opp_put_supported_hw(hw_opp_table);
 put_clk_table:
 	dev_pm_opp_put_clkname(clk_opp_table);
-put_reg_table:
-	if (reg_opp_table)
-		dev_pm_opp_put_regulators(reg_opp_table);
 
 	return err;
 }
-- 
2.29.2

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2020-11-23  0:32 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20201123003254epcas1p1763e1ce693d7cb8e2f20d521e701ad5f@epcas1p1.samsung.com>
2020-11-23  0:27 ` [PATCH v10 00/19] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-11-23  0:27   ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 01/19] dt-bindings: memory: tegra20: emc: Document opp-supported-hw property Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-30  9:48     ` Georgi Djakov
2020-11-30  9:48       ` Georgi Djakov
2020-11-30 18:23       ` Krzysztof Kozlowski
2020-11-30 18:23         ` Krzysztof Kozlowski
2020-11-30 20:03         ` Dmitry Osipenko
2020-11-30 20:03           ` Dmitry Osipenko
2020-11-23  0:27   ` Dmitry Osipenko [this message]
2020-11-23  0:27     ` [PATCH v10 02/19] memory: tegra20: Support hardware versioning and clean up OPP table initialization Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 03/19] memory: tegra30: Support interconnect framework Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  6:32     ` Georgi Djakov
2020-11-23  6:32       ` Georgi Djakov
2020-11-23 12:14       ` Dmitry Osipenko
2020-11-23 12:14         ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 04/19] memory: tegra124-emc: Make driver modular Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 05/19] memory: tegra124-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 06/19] memory: tegra124: Support interconnect framework Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  6:33     ` Georgi Djakov
2020-11-23  6:33       ` Georgi Djakov
2020-11-23  0:27   ` [PATCH v10 07/19] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 08/19] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 09/19] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  7:02     ` Chanwoo Choi
2020-11-23  7:02       ` Chanwoo Choi
2020-11-23 12:14       ` Dmitry Osipenko
2020-11-23 12:14         ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 10/19] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 11/19] PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  7:02     ` Chanwoo Choi
2020-11-23  7:02       ` Chanwoo Choi
2020-11-23  0:27   ` [PATCH v10 12/19] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 13/19] ARM: tegra: Add interconnect properties to " Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 14/19] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 15/19] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 16/19] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko
2020-11-23  0:27     ` [PATCH v10 16/19] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 17/19] ARM: tegra: Add EMC OPP properties to Tegra20 device-trees Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-30 21:17     ` Jon Hunter
2020-11-30 21:17       ` Jon Hunter
2020-11-30 22:57       ` Dmitry Osipenko
2020-11-30 22:57         ` Dmitry Osipenko
2020-12-01 20:42         ` Jon Hunter
2020-12-01 20:42           ` Jon Hunter
2020-12-04 15:54         ` Thierry Reding
2020-12-04 15:54           ` Thierry Reding
2020-12-05 13:52           ` Krzysztof Kozlowski
2020-12-05 13:52             ` Krzysztof Kozlowski
2020-11-23  0:27   ` [PATCH v10 18/19] ARM: tegra: Add EMC OPP and ICC properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  0:27   ` [PATCH v10 19/19] ARM: tegra: Add EMC OPP and ICC properties to Tegra124 " Dmitry Osipenko
2020-11-23  0:27     ` Dmitry Osipenko
2020-11-23  6:17   ` [PATCH v10 00/19] Introduce memory interconnect for NVIDIA Tegra SoCs Viresh Kumar
2020-11-23  6:17     ` Viresh Kumar
2020-11-23 12:13     ` Dmitry Osipenko
2020-11-23 12:13       ` Dmitry Osipenko
2020-11-30  8:44   ` Chanwoo Choi
2020-11-30  8:44     ` Chanwoo Choi
2020-11-30  8:36     ` Krzysztof Kozlowski
2020-11-30  8:36       ` Krzysztof Kozlowski
2020-11-30  8:59       ` Chanwoo Choi
2020-11-30  8:59         ` Chanwoo Choi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201123002723.28463-3-digetx@gmail.com \
    --to=digetx@gmail.com \
    --cc=cw00.choi@samsung.com \
    --cc=cyndis@kapsi.fi \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=georgi.djakov@linaro.org \
    --cc=jonathanh@nvidia.com \
    --cc=krzk@kernel.org \
    --cc=kwizart@gmail.com \
    --cc=kyungmin.park@samsung.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=myungjoo.ham@samsung.com \
    --cc=pdeschrijver@nvidia.com \
    --cc=pgwipeout@gmail.com \
    --cc=robh+dt@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=thierry.reding@gmail.com \
    --cc=vireshk@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.