From: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
To: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] arm64: dts: renesas: r8a77951: Add PCIe EP nodes
Date: Wed, 25 Nov 2020 16:33:03 +0900 [thread overview]
Message-ID: <20201125073303.19057-3-yuya.hamamachi.sx@renesas.com> (raw)
In-Reply-To: <20201125073303.19057-1-yuya.hamamachi.sx@renesas.com>
Add PCIe EP nodes for R8A77951 SoC dtsi.
Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a77951.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 644308dd886c..9d60bcf69e4f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -2727,6 +2727,44 @@ pciec1: pcie@ee800000 {
status = "disabled";
};
+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a7795-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a7795-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
imr-lx4@fe860000 {
compatible = "renesas,r8a7795-imr-lx4",
"renesas,imr-lx4";
--
2.25.1
next prev parent reply other threads:[~2020-11-25 7:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 7:33 [PATCH 0/2] Add PCIe EP to R-Car H3 Yuya Hamamachi
2020-11-25 7:33 ` [PATCH 1/2] dt-bindings: pci: rcar-pci-ep: Document r8a7795 Yuya Hamamachi
2020-11-26 10:51 ` Geert Uytterhoeven
2020-11-25 7:33 ` Yuya Hamamachi [this message]
2020-11-26 11:43 ` [PATCH 2/2] arm64: dts: renesas: r8a77951: Add PCIe EP nodes Geert Uytterhoeven
-- strict thread matches above, loose matches on Subject: below --
2020-11-24 5:42 [PATCH 0/2] Add PCIe EP to R-Car H3 Yuya Hamamachi
2020-11-24 5:42 ` [PATCH 2/2] arm64: dts: renesas: r8a77951: Add PCIe EP nodes Yuya Hamamachi
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