From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, Karthik B S <karthik.b.s@intel.com>, uma.shankar@intel.com, seanpaul@chromium.org, Anshuman Gupta <anshuman.gupta@intel.com>, juston.li@intel.com Subject: [PATCH v6 16/18] drm/i915/hdcp: Add HDCP 2.2 stream register Date: Thu, 26 Nov 2020 13:07:20 +0530 [thread overview] Message-ID: <20201126073722.19107-17-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201126073722.19107-1-anshuman.gupta@intel.com> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c8e5853731c4..a74602172861 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9872,6 +9872,7 @@ enum skl_power_gate { _PORTD_HDCP2_BASE, \ _PORTE_HDCP2_BASE, \ _PORTF_HDCP2_BASE) + (x)) + #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) #define _TRANSA_HDCP2_AUTH 0x66498 #define _TRANSB_HDCP2_AUTH 0x66598 @@ -9911,6 +9912,35 @@ enum skl_power_gate { TRANS_HDCP2_STATUS(trans) : \ PORT_HDCP2_STATUS(port)) +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_STREAM_STATUS, \ + _TRANSB_HDCP2_STREAM_STATUS) +#define STREAM_ENCRYPTION_STATUS BIT(31) +#define STREAM_TYPE_STATUS BIT(30) +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_STREAM_STATUS(trans) : \ + PORT_HDCP2_STREAM_STATUS(port)) + +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ + _PORTA_HDCP2_AUTH_STREAM, \ + _PORTB_HDCP2_AUTH_STREAM) +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_AUTH_STREAM, \ + _TRANSB_HDCP2_AUTH_STREAM) +#define AUTH_STREAM_TYPE BIT(31) +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_AUTH_STREAM(trans) : \ + PORT_HDCP2_AUTH_STREAM(port)) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
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From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, seanpaul@chromium.org Subject: [Intel-gfx] [PATCH v6 16/18] drm/i915/hdcp: Add HDCP 2.2 stream register Date: Thu, 26 Nov 2020 13:07:20 +0530 [thread overview] Message-ID: <20201126073722.19107-17-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201126073722.19107-1-anshuman.gupta@intel.com> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c8e5853731c4..a74602172861 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9872,6 +9872,7 @@ enum skl_power_gate { _PORTD_HDCP2_BASE, \ _PORTE_HDCP2_BASE, \ _PORTF_HDCP2_BASE) + (x)) + #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) #define _TRANSA_HDCP2_AUTH 0x66498 #define _TRANSB_HDCP2_AUTH 0x66598 @@ -9911,6 +9912,35 @@ enum skl_power_gate { TRANS_HDCP2_STATUS(trans) : \ PORT_HDCP2_STATUS(port)) +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_STREAM_STATUS, \ + _TRANSB_HDCP2_STREAM_STATUS) +#define STREAM_ENCRYPTION_STATUS BIT(31) +#define STREAM_TYPE_STATUS BIT(30) +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_STREAM_STATUS(trans) : \ + PORT_HDCP2_STREAM_STATUS(port)) + +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ + _PORTA_HDCP2_AUTH_STREAM, \ + _PORTB_HDCP2_AUTH_STREAM) +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_AUTH_STREAM, \ + _TRANSB_HDCP2_AUTH_STREAM) +#define AUTH_STREAM_TYPE BIT(31) +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_AUTH_STREAM(trans) : \ + PORT_HDCP2_AUTH_STREAM(port)) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-11-26 7:52 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-26 7:37 [PATCH v6 00/18] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 01/18] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 02/18] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 03/18] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 04/18] drm/i915/hdcp: No HDCP when encoder is't initialized Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 9:02 ` Ramalingam C 2020-12-04 9:02 ` [Intel-gfx] " Ramalingam C 2020-12-04 8:58 ` Anshuman Gupta 2020-12-04 8:58 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 05/18] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 06/18] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 07/18] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 08/18] drm/i915/hdcp: Enable HDCP 1.4 stream encryption Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 09/18] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 10/18] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 11/18] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 12/18] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 13/18] drm/hdcp: Max MST content streams Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 14/18] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 15/18] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` Anshuman Gupta [this message] 2020-11-26 7:37 ` [Intel-gfx] [PATCH v6 16/18] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 17/18] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 7:37 ` [PATCH v6 18/18] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta 2020-11-26 7:37 ` [Intel-gfx] " Anshuman Gupta 2020-11-26 10:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev5) Patchwork 2020-11-26 10:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-11-26 10:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-11-26 12:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-11-27 5:36 ` [Intel-gfx] [PATCH v6 00/18] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Karthik B S 2020-11-27 5:36 ` Karthik B S
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