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From: Andrew Jones <drjones@redhat.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, pbonzini@redhat.com
Subject: [PATCH 1/2] KVM: arm64: CSSELR_EL1 max is 13
Date: Thu, 26 Nov 2020 14:46:40 +0100	[thread overview]
Message-ID: <20201126134641.35231-2-drjones@redhat.com> (raw)
In-Reply-To: <20201126134641.35231-1-drjones@redhat.com>

Not counting TnD, which KVM doesn't currently consider, CSSELR_EL1
can have a maximum value of 0b1101 (13), which corresponds to an
instruction cache at level 7. With CSSELR_MAX set to 12 we can
only select up to cache level 6. Change it to 14.

Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 arch/arm64/kvm/sys_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c1fac9836af1..ef453f7827fa 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -169,7 +169,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 static u32 cache_levels;
 
 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
-#define CSSELR_MAX 12
+#define CSSELR_MAX 14
 
 /* Which cache CCSIDR represents depends on CSSELR value. */
 static u32 get_ccsidr(u32 csselr)
-- 
2.26.2


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <drjones@redhat.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, pbonzini@redhat.com
Subject: [PATCH 1/2] KVM: arm64: CSSELR_EL1 max is 13
Date: Thu, 26 Nov 2020 14:46:40 +0100	[thread overview]
Message-ID: <20201126134641.35231-2-drjones@redhat.com> (raw)
In-Reply-To: <20201126134641.35231-1-drjones@redhat.com>

Not counting TnD, which KVM doesn't currently consider, CSSELR_EL1
can have a maximum value of 0b1101 (13), which corresponds to an
instruction cache at level 7. With CSSELR_MAX set to 12 we can
only select up to cache level 6. Change it to 14.

Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 arch/arm64/kvm/sys_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c1fac9836af1..ef453f7827fa 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -169,7 +169,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 static u32 cache_levels;
 
 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
-#define CSSELR_MAX 12
+#define CSSELR_MAX 14
 
 /* Which cache CCSIDR represents depends on CSSELR value. */
 static u32 get_ccsidr(u32 csselr)
-- 
2.26.2

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  reply	other threads:[~2020-11-26 13:47 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26 13:46 [PATCH 0/2] KVM: arm64: Fix DEMUX register access Andrew Jones
2020-11-26 13:46 ` Andrew Jones
2020-11-26 13:46 ` Andrew Jones [this message]
2020-11-26 13:46   ` [PATCH 1/2] KVM: arm64: CSSELR_EL1 max is 13 Andrew Jones
2020-11-26 14:13   ` Marc Zyngier
2020-11-26 14:13     ` Marc Zyngier
2020-11-26 14:32     ` Andrew Jones
2020-11-26 14:32       ` Andrew Jones
2020-11-26 14:34       ` Marc Zyngier
2020-11-26 14:34         ` Marc Zyngier
2020-11-26 14:36         ` Andrew Jones
2020-11-26 14:36           ` Andrew Jones
2020-11-26 13:46 ` [PATCH 2/2] KVM: selftests: Filter out DEMUX registers Andrew Jones
2020-11-26 13:46   ` Andrew Jones
2020-11-27 19:47 ` [PATCH 0/2] KVM: arm64: Fix DEMUX register access Marc Zyngier
2020-11-27 19:47   ` Marc Zyngier

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