From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI] drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register def
Date: Wed, 2 Dec 2020 10:27:27 -0800 [thread overview]
Message-ID: <20201202182727.26158-1-manasi.d.navare@intel.com> (raw)
VRR_CTL register only had a GENMASK but no field prep
define for TRANS_VRR_CTL_LINE_COUNT field so add that
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cdc67f583a9c..0023c023f472 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4352,6 +4352,7 @@ enum {
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_LINE_COUNT(x) REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
#define _TRANS_VRR_VMAX_A 0x60424
--
2.19.1
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next reply other threads:[~2020-12-02 18:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 18:27 Manasi Navare [this message]
2020-12-02 19:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register def Patchwork
2020-12-02 23:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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