From: "Philippe Mathieu-Daudé" <f4bug@amsat.org> To: qemu-devel@nongnu.org Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>, "Huacai Chen" <chenhc@lemote.com>, "Richard Henderson" <richard.henderson@linaro.org>, kvm@vger.kernel.org, "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Aurelien Jarno" <aurelien@aurel32.net>, "Philippe Mathieu-Daudé" <f4bug@amsat.org> Subject: [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Wed, 2 Dec 2020 19:44:13 +0100 [thread overview] Message-ID: <20201202184415.1434484-8-f4bug@amsat.org> (raw) In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org> Extract the logic initialization of the MSA registers from the generic initialization. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 41880f21abd..a5112acc351 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31672,6 +31672,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } +static void msa_translate_init(void) +{ + int i; + + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] = fpu_f64[i]; + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] = + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); + } +} + void mips_tcg_init(void) { int i; @@ -31685,22 +31703,9 @@ void mips_tcg_init(void) for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] = fpu_f64[i]; - off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] = - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); - } - + msa_translate_init(); cpu_PC = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"); for (i = 0; i < MIPS_DSP_ACC; i++) { -- 2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org> To: qemu-devel@nongnu.org Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>, kvm@vger.kernel.org, "Richard Henderson" <richard.henderson@linaro.org>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Paolo Bonzini" <pbonzini@redhat.com>, "Huacai Chen" <chenhc@lemote.com>, "Aurelien Jarno" <aurelien@aurel32.net> Subject: [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Wed, 2 Dec 2020 19:44:13 +0100 [thread overview] Message-ID: <20201202184415.1434484-8-f4bug@amsat.org> (raw) In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org> Extract the logic initialization of the MSA registers from the generic initialization. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 41880f21abd..a5112acc351 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31672,6 +31672,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } +static void msa_translate_init(void) +{ + int i; + + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] = fpu_f64[i]; + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] = + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); + } +} + void mips_tcg_init(void) { int i; @@ -31685,22 +31703,9 @@ void mips_tcg_init(void) for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] = fpu_f64[i]; - off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] = - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); - } - + msa_translate_init(); cpu_PC = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"); for (i = 0; i < MIPS_DSP_ACC; i++) { -- 2.26.2
next prev parent reply other threads:[~2020-12-02 18:45 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-02 18:44 [PATCH 0/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-02 18:44 ` [PATCH 1/9] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-03 17:08 ` Richard Henderson 2020-12-03 17:08 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 2/9] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-03 17:10 ` Richard Henderson 2020-12-03 17:10 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-03 17:10 ` Richard Henderson 2020-12-03 17:10 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 4/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-03 17:14 ` Richard Henderson 2020-12-03 17:14 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-03 17:15 ` Richard Henderson 2020-12-03 17:15 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-04 16:28 ` Richard Henderson 2020-12-04 16:28 ` Richard Henderson 2020-12-04 22:40 ` Philippe Mathieu-Daudé 2020-12-04 22:40 ` Philippe Mathieu-Daudé 2020-12-05 12:44 ` Richard Henderson 2020-12-05 12:44 ` Richard Henderson 2020-12-02 18:44 ` Philippe Mathieu-Daudé [this message] 2020-12-02 18:44 ` [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé 2020-12-04 16:30 ` Richard Henderson 2020-12-04 16:30 ` Richard Henderson 2020-12-04 17:23 ` Philippe Mathieu-Daudé 2020-12-04 17:23 ` Philippe Mathieu-Daudé 2020-12-04 18:15 ` Richard Henderson 2020-12-04 18:15 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-04 16:31 ` Richard Henderson 2020-12-04 16:31 ` Richard Henderson 2020-12-02 18:44 ` [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé 2020-12-02 18:44 ` Philippe Mathieu-Daudé 2020-12-04 17:04 ` Richard Henderson 2020-12-04 17:04 ` Richard Henderson 2020-12-04 22:53 ` Philippe Mathieu-Daudé 2020-12-04 22:53 ` Philippe Mathieu-Daudé 2020-12-05 12:46 ` Richard Henderson 2020-12-05 12:46 ` Richard Henderson 2020-12-03 3:36 ` [PATCH 0/9] target/mips: Simplify MSA TCG logic Jiaxun Yang 2020-12-03 3:36 ` Jiaxun Yang 2020-12-03 3:38 ` Jiaxun Yang 2020-12-03 3:38 ` Jiaxun Yang
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