From: Alexander Graf <agraf@csgraf.de>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Eduardo Habkost <ehabkost@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Cameron Esfahani <dirty@apple.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
qemu-arm@nongnu.org, Frank Yang <lfy@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Collingbourne <pcc@google.com>
Subject: [PATCH v4 10/11] hvf: arm: Add support for GICv3
Date: Fri, 4 Dec 2020 00:48:56 +0100 [thread overview]
Message-ID: <20201203234857.21051-11-agraf@csgraf.de> (raw)
In-Reply-To: <20201203234857.21051-1-agraf@csgraf.de>
We currently only support GICv2 emulation. To also support GICv3, we will
need to pass a few system registers into their respective handler functions.
This patch adds handling for all of the required system registers, so that
we can run with more than 8 vCPUs.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
---
target/arm/hvf/hvf.c | 141 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 979008e188..bc955c097f 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -22,6 +22,7 @@
#include "exec/address-spaces.h"
#include "hw/irq.h"
+#include "hw/intc/gicv3_internal.h"
#include "qemu/main-loop.h"
#include "sysemu/accel.h"
#include "sysemu/cpus.h"
@@ -46,6 +47,33 @@
#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 1, 14, 0)
#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 0, 9, 13)
+#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 4, 12, 8)
+#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 5, 12, 8)
+#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 6, 12, 8)
+#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 7, 12, 8)
+#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 0, 12, 9)
+#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 1, 12, 9)
+#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 2, 12, 9)
+#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 3, 12, 9)
+#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 6, 12, 11)
+#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 3, 12, 8)
+#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 3, 12, 12)
+#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 4, 12, 12)
+#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 1, 12, 11)
+#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 1, 12, 8)
+#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 1, 12, 12)
+#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 2, 12, 8)
+#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 2, 12, 12)
+#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 0, 12, 8)
+#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 0, 12, 12)
+#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 6, 12, 12)
+#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 7, 12, 12)
+#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 0, 4, 6)
+#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 3, 12, 11)
+#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 7, 12, 11)
+#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 5, 12, 11)
+#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 5, 12, 12)
+
#define WFX_IS_WFE (1 << 0)
struct hvf_reg_match {
@@ -418,6 +446,38 @@ void hvf_kick_vcpu_thread(CPUState *cpu)
hv_vcpus_exit(&cpu->hvf->fd, 1);
}
+static uint32_t hvf_reg2cp_reg(uint32_t reg)
+{
+ return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
+ (reg >> 10) & 0xf,
+ (reg >> 1) & 0xf,
+ (reg >> 20) & 0x3,
+ (reg >> 14) & 0x7,
+ (reg >> 17) & 0x7);
+}
+
+static uint64_t hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ const ARMCPRegInfo *ri;
+ uint64_t val = 0;
+
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+ if (ri) {
+ if (ri->type & ARM_CP_CONST) {
+ val = ri->resetvalue;
+ } else if (ri->readfn) {
+ val = ri->readfn(env, ri);
+ } else {
+ val = CPREG_FIELD64(env, ri);
+ }
+ DPRINTF("vgic read from %s [val=%016llx]", ri->name, val);
+ }
+
+ return val;
+}
+
static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -431,6 +491,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)
case SYSREG_PMCCNTR_EL0:
val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
break;
+ case SYSREG_ICC_AP0R0_EL1:
+ case SYSREG_ICC_AP0R1_EL1:
+ case SYSREG_ICC_AP0R2_EL1:
+ case SYSREG_ICC_AP0R3_EL1:
+ case SYSREG_ICC_AP1R0_EL1:
+ case SYSREG_ICC_AP1R1_EL1:
+ case SYSREG_ICC_AP1R2_EL1:
+ case SYSREG_ICC_AP1R3_EL1:
+ case SYSREG_ICC_ASGI1R_EL1:
+ case SYSREG_ICC_BPR0_EL1:
+ case SYSREG_ICC_BPR1_EL1:
+ case SYSREG_ICC_DIR_EL1:
+ case SYSREG_ICC_EOIR0_EL1:
+ case SYSREG_ICC_EOIR1_EL1:
+ case SYSREG_ICC_HPPIR0_EL1:
+ case SYSREG_ICC_HPPIR1_EL1:
+ case SYSREG_ICC_IAR0_EL1:
+ case SYSREG_ICC_IAR1_EL1:
+ case SYSREG_ICC_IGRPEN0_EL1:
+ case SYSREG_ICC_IGRPEN1_EL1:
+ case SYSREG_ICC_PMR_EL1:
+ case SYSREG_ICC_SGI0R_EL1:
+ case SYSREG_ICC_SGI1R_EL1:
+ case SYSREG_ICC_SRE_EL1:
+ val = hvf_sysreg_read_cp(cpu, reg);
+ break;
+ case SYSREG_ICC_CTLR_EL1:
+ val = hvf_sysreg_read_cp(cpu, reg);
+
+ /* AP0R registers above 0 don't trap, expose less PRIs to fit */
+ val &= ~ICC_CTLR_EL1_PRIBITS_MASK;
+ val |= 4 << ICC_CTLR_EL1_PRIBITS_SHIFT;
+ break;
default:
DPRINTF("unhandled sysreg read %08x (op0=%d op1=%d op2=%d "
"crn=%d crm=%d)", reg, (reg >> 20) & 0x3,
@@ -442,6 +535,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)
return val;
}
+static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ const ARMCPRegInfo *ri;
+
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+
+ if (ri) {
+ if (ri->writefn) {
+ ri->writefn(env, ri, val);
+ } else {
+ CPREG_FIELD64(env, ri) = val;
+ }
+ DPRINTF("vgic write to %s [val=%016llx]", ri->name, val);
+ }
+}
+
static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -449,6 +560,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
switch (reg) {
case SYSREG_CNTPCT_EL0:
break;
+ case SYSREG_ICC_AP0R0_EL1:
+ case SYSREG_ICC_AP0R1_EL1:
+ case SYSREG_ICC_AP0R2_EL1:
+ case SYSREG_ICC_AP0R3_EL1:
+ case SYSREG_ICC_AP1R0_EL1:
+ case SYSREG_ICC_AP1R1_EL1:
+ case SYSREG_ICC_AP1R2_EL1:
+ case SYSREG_ICC_AP1R3_EL1:
+ case SYSREG_ICC_ASGI1R_EL1:
+ case SYSREG_ICC_BPR0_EL1:
+ case SYSREG_ICC_BPR1_EL1:
+ case SYSREG_ICC_CTLR_EL1:
+ case SYSREG_ICC_DIR_EL1:
+ case SYSREG_ICC_HPPIR0_EL1:
+ case SYSREG_ICC_HPPIR1_EL1:
+ case SYSREG_ICC_IAR0_EL1:
+ case SYSREG_ICC_IAR1_EL1:
+ case SYSREG_ICC_IGRPEN0_EL1:
+ case SYSREG_ICC_IGRPEN1_EL1:
+ case SYSREG_ICC_PMR_EL1:
+ case SYSREG_ICC_SGI0R_EL1:
+ case SYSREG_ICC_SGI1R_EL1:
+ case SYSREG_ICC_SRE_EL1:
+ hvf_sysreg_write_cp(cpu, reg, val);
+ break;
+ case SYSREG_ICC_EOIR0_EL1:
+ case SYSREG_ICC_EOIR1_EL1:
+ hvf_sysreg_write_cp(cpu, reg, val);
+ qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0);
+ hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);
default:
DPRINTF("unhandled sysreg write %08x", reg);
break;
--
2.24.3 (Apple Git-128)
next prev parent reply other threads:[~2020-12-03 23:55 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 23:48 [PATCH v4 00/11] hvf: Implement Apple Silicon Support Alexander Graf
2020-12-03 23:48 ` [PATCH v4 01/11] hvf: Add hypervisor entitlement to output binaries Alexander Graf
2020-12-04 14:50 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 02/11] hvf: x86: Remove unused definitions Alexander Graf
2020-12-04 14:51 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 03/11] hvf: Move common code out Alexander Graf
2020-12-04 14:55 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 04/11] hvf: Introduce hvf vcpu struct Alexander Graf
2020-12-04 16:15 ` Alex Bennée
2020-12-03 23:48 ` [PATCH v4 05/11] arm: Set PSCI to 0.2 for HVF Alexander Graf
2020-12-04 14:56 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 06/11] hvf: Simplify post reset/init/loadvm hooks Alexander Graf
2020-12-04 16:07 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 07/11] hvf: Add Apple Silicon support Alexander Graf
2020-12-04 16:41 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 08/11] arm: Add Hypervisor.framework build target Alexander Graf
2020-12-04 16:25 ` Alex Bennée
2020-12-04 16:44 ` Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 09/11] arm/hvf: Add a WFI handler Alexander Graf
2020-12-04 16:45 ` Roman Bolshakov
2020-12-03 23:48 ` Alexander Graf [this message]
2020-12-04 16:46 ` [PATCH v4 10/11] hvf: arm: Add support for GICv3 Roman Bolshakov
2020-12-03 23:48 ` [PATCH v4 11/11] hvf: arm: Implement -cpu host Alexander Graf
2020-12-04 16:47 ` Roman Bolshakov
2020-12-04 0:03 ` [PATCH v4 00/11] hvf: Implement Apple Silicon Support no-reply
2020-12-04 16:55 ` Roman Bolshakov
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