From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: swati2.sharma@intel.com, airlied@linux.ie, vandita.kulkarni@intel.com, uma.shankar@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH v5 08/15] drm/i915: Capture max frl rate for PCON in dfp cap structure Date: Wed, 16 Dec 2020 11:01:14 +0530 [thread overview] Message-ID: <20201216053121.18819-9-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201216053121.18819-1-ankit.k.nautiyal@intel.com> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON. This patch captures this in dfp cap structure in intel_dp and uses this to prune connector modes that cannot be supported by the PCON and FRL bandwidth. v2: Addressed review comments from Uma Shankar: -tweaked the comparison of target bw and pcon frl bw to avoid roundup errors. -minor modification of field names and comments. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5bc5bfbc4551..c88d2b918d9f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1451,6 +1451,7 @@ struct intel_dp { struct { int min_tmds_clock, max_tmds_clock; int max_dotclock; + int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb5e42c3ecd5..660b4bd2280a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -716,6 +716,25 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; int tmds_clock; + /* If PCON supports FRL MODE, check FRL bandwidth constraints */ + if (intel_dp->dfp.pcon_max_frl_bw) { + int target_bw; + int max_frl_bw; + int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode); + + target_bw = bpp * target_clock; + + max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; + } + if (intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; @@ -6484,13 +6503,18 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->downstream_ports, edid); + intel_dp->dfp.pcon_max_frl_bw = + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, + intel_dp->downstream_ports); + drm_dbg_kms(&i915->drm, - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", connector->base.base.id, connector->base.name, intel_dp->dfp.max_bpc, intel_dp->dfp.max_dotclock, intel_dp->dfp.min_tmds_clock, - intel_dp->dfp.max_tmds_clock); + intel_dp->dfp.max_tmds_clock, + intel_dp->dfp.pcon_max_frl_bw); } static void @@ -6582,6 +6606,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->dfp.min_tmds_clock = 0; intel_dp->dfp.max_tmds_clock = 0; + intel_dp->dfp.pcon_max_frl_bw = 0; + intel_dp->dfp.ycbcr_444_to_420 = false; connector->base.ycbcr_420_allowed = false; } -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v5 08/15] drm/i915: Capture max frl rate for PCON in dfp cap structure Date: Wed, 16 Dec 2020 11:01:14 +0530 [thread overview] Message-ID: <20201216053121.18819-9-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201216053121.18819-1-ankit.k.nautiyal@intel.com> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON. This patch captures this in dfp cap structure in intel_dp and uses this to prune connector modes that cannot be supported by the PCON and FRL bandwidth. v2: Addressed review comments from Uma Shankar: -tweaked the comparison of target bw and pcon frl bw to avoid roundup errors. -minor modification of field names and comments. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5bc5bfbc4551..c88d2b918d9f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1451,6 +1451,7 @@ struct intel_dp { struct { int min_tmds_clock, max_tmds_clock; int max_dotclock; + int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb5e42c3ecd5..660b4bd2280a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -716,6 +716,25 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; int tmds_clock; + /* If PCON supports FRL MODE, check FRL bandwidth constraints */ + if (intel_dp->dfp.pcon_max_frl_bw) { + int target_bw; + int max_frl_bw; + int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode); + + target_bw = bpp * target_clock; + + max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; + } + if (intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; @@ -6484,13 +6503,18 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->downstream_ports, edid); + intel_dp->dfp.pcon_max_frl_bw = + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, + intel_dp->downstream_ports); + drm_dbg_kms(&i915->drm, - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", connector->base.base.id, connector->base.name, intel_dp->dfp.max_bpc, intel_dp->dfp.max_dotclock, intel_dp->dfp.min_tmds_clock, - intel_dp->dfp.max_tmds_clock); + intel_dp->dfp.max_tmds_clock, + intel_dp->dfp.pcon_max_frl_bw); } static void @@ -6582,6 +6606,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->dfp.min_tmds_clock = 0; intel_dp->dfp.max_tmds_clock = 0; + intel_dp->dfp.pcon_max_frl_bw = 0; + intel_dp->dfp.ycbcr_444_to_420 = false; connector->base.ycbcr_420_allowed = false; } -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-16 5:38 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-16 5:31 [PATCH v5 00/15] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 01/15] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 02/15] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 03/15] drm/edid: Parse DSC1.2 cap fields " Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 04/15] drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 05/15] drm/dp_helper: Add support for link failure detection Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 06/15] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 07/15] drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 19:15 ` Shankar, Uma 2020-12-16 19:15 ` [Intel-gfx] " Shankar, Uma 2020-12-16 5:31 ` Ankit Nautiyal [this message] 2020-12-16 5:31 ` [Intel-gfx] [PATCH v5 08/15] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 09/15] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 10/15] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 11/15] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 12/15] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 13/15] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 14/15] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 5:31 ` [PATCH v5 15/15] drm/i915/display: Let PCON convert from RGB to YUV if it can Ankit Nautiyal 2020-12-16 5:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 11:31 ` [PATCH v6 " Ankit Nautiyal 2020-12-16 11:31 ` [Intel-gfx] " Ankit Nautiyal 2020-12-16 19:33 ` Shankar, Uma 2020-12-16 19:33 ` [Intel-gfx] " Shankar, Uma 2020-12-16 6:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev7) Patchwork 2020-12-16 6:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-16 6:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-16 9:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-12-16 13:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev8) Patchwork 2020-12-16 13:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-16 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-16 15:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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