From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: swati2.sharma@intel.com, airlied@linux.ie, vandita.kulkarni@intel.com, uma.shankar@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH v7 01/15] drm/edid: Add additional HFVSDB fields for HDMI2.1 Date: Fri, 18 Dec 2020 16:07:09 +0530 [thread overview] Message-ID: <20201218103723.30844-2-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201218103723.30844-1-ankit.k.nautiyal@intel.com> From: Swati Sharma <swati2.sharma@intel.com> The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific Data block) to have fields related to newly defined methods of FRL (Fixed Rate Link) levels, number of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM etc. This patch adds the new HFVSDB fields that are required for HDMI2.1. v2: Minor fixes + consistent naming for DPCD register masks (Uma Shankar) Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index e97daf6ffbb1..a158f585f658 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -229,6 +229,36 @@ struct detailed_timing { DRM_EDID_YCBCR420_DC_36 | \ DRM_EDID_YCBCR420_DC_30) +/* HDMI 2.1 additional fields */ +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_FAPA_START_LOCATION (1 << 0) +#define DRM_EDID_ALLM (1 << 1) +#define DRM_EDID_FVA (1 << 2) + +/* Deep Color specific */ +#define DRM_EDID_DC_30BIT_420 (1 << 0) +#define DRM_EDID_DC_36BIT_420 (1 << 1) +#define DRM_EDID_DC_48BIT_420 (1 << 2) + +/* VRR specific */ +#define DRM_EDID_CNMVRR (1 << 3) +#define DRM_EDID_CINEMA_VRR (1 << 4) +#define DRM_EDID_MDELTA (1 << 5) +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff +#define DRM_EDID_VRR_MIN_MASK 0x3f + +/* DSC specific */ +#define DRM_EDID_DSC_10BPC (1 << 0) +#define DRM_EDID_DSC_12BPC (1 << 1) +#define DRM_EDID_DSC_16BPC (1 << 2) +#define DRM_EDID_DSC_ALL_BPP (1 << 3) +#define DRM_EDID_DSC_NATIVE_420 (1 << 6) +#define DRM_EDID_DSC_1P2 (1 << 7) +#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_DSC_MAX_SLICES 0xf +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4 -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
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From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v7 01/15] drm/edid: Add additional HFVSDB fields for HDMI2.1 Date: Fri, 18 Dec 2020 16:07:09 +0530 [thread overview] Message-ID: <20201218103723.30844-2-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201218103723.30844-1-ankit.k.nautiyal@intel.com> From: Swati Sharma <swati2.sharma@intel.com> The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific Data block) to have fields related to newly defined methods of FRL (Fixed Rate Link) levels, number of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM etc. This patch adds the new HFVSDB fields that are required for HDMI2.1. v2: Minor fixes + consistent naming for DPCD register masks (Uma Shankar) Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index e97daf6ffbb1..a158f585f658 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -229,6 +229,36 @@ struct detailed_timing { DRM_EDID_YCBCR420_DC_36 | \ DRM_EDID_YCBCR420_DC_30) +/* HDMI 2.1 additional fields */ +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_FAPA_START_LOCATION (1 << 0) +#define DRM_EDID_ALLM (1 << 1) +#define DRM_EDID_FVA (1 << 2) + +/* Deep Color specific */ +#define DRM_EDID_DC_30BIT_420 (1 << 0) +#define DRM_EDID_DC_36BIT_420 (1 << 1) +#define DRM_EDID_DC_48BIT_420 (1 << 2) + +/* VRR specific */ +#define DRM_EDID_CNMVRR (1 << 3) +#define DRM_EDID_CINEMA_VRR (1 << 4) +#define DRM_EDID_MDELTA (1 << 5) +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff +#define DRM_EDID_VRR_MIN_MASK 0x3f + +/* DSC specific */ +#define DRM_EDID_DSC_10BPC (1 << 0) +#define DRM_EDID_DSC_12BPC (1 << 1) +#define DRM_EDID_DSC_16BPC (1 << 2) +#define DRM_EDID_DSC_ALL_BPP (1 << 3) +#define DRM_EDID_DSC_NATIVE_420 (1 << 6) +#define DRM_EDID_DSC_1P2 (1 << 7) +#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_DSC_MAX_SLICES 0xf +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4 -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-18 10:43 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-18 10:37 [PATCH v7 00/15] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` Ankit Nautiyal [this message] 2020-12-18 10:37 ` [Intel-gfx] [PATCH v7 01/15] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 02/15] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 03/15] drm/edid: Parse DSC1.2 cap fields " Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 04/15] drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 11:05 ` Shankar, Uma 2020-12-18 11:05 ` [Intel-gfx] " Shankar, Uma 2020-12-18 10:37 ` [PATCH v7 05/15] drm/dp_helper: Add support for link failure detection Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 06/15] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 07/15] drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 08/15] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 09/15] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2021-02-01 20:38 ` Ville Syrjälä 2021-02-01 20:38 ` [Intel-gfx] " Ville Syrjälä 2021-02-02 6:39 ` Nautiyal, Ankit K 2021-02-02 6:39 ` [Intel-gfx] " Nautiyal, Ankit K 2021-02-02 6:47 ` Ville Syrjälä 2021-02-02 6:47 ` [Intel-gfx] " Ville Syrjälä 2021-02-02 8:11 ` Nautiyal, Ankit K 2021-02-02 8:11 ` [Intel-gfx] " Nautiyal, Ankit K 2020-12-18 10:37 ` [PATCH v7 10/15] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 11/15] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 11:06 ` Shankar, Uma 2020-12-18 11:06 ` [Intel-gfx] " Shankar, Uma 2020-12-18 10:37 ` [PATCH v7 12/15] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 13/15] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 14/15] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 10:37 ` [PATCH v7 15/15] drm/i915/display: Let PCON convert from RGB to YCbCr if it can Ankit Nautiyal 2020-12-18 10:37 ` [Intel-gfx] " Ankit Nautiyal 2020-12-18 11:11 ` Shankar, Uma 2020-12-18 11:11 ` [Intel-gfx] " Shankar, Uma 2020-12-18 12:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev9) Patchwork 2020-12-22 16:43 ` Jani Nikula 2020-12-23 5:56 ` Nautiyal, Ankit K 2020-12-23 6:54 ` Shankar, Uma 2020-12-23 7:08 ` Sharma, Swati2 2020-12-23 9:18 ` Jani Nikula 2020-12-18 12:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-18 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-18 15:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-12-22 16:28 ` [PATCH v7 00/15] Add support for DP-HDMI2.1 PCON Jani Nikula 2020-12-22 16:28 ` [Intel-gfx] " Jani Nikula
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