From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec
Date: Fri, 25 Dec 2020 12:19:55 -0800 [thread overview]
Message-ID: <20201225201956.692861-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201225201956.692861-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-conset.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target-conset.h b/tcg/s390x/tcg-target-conset.h
index 9c7dd85eac..4890dbf807 100644
--- a/tcg/s390x/tcg-target-conset.h
+++ b/tcg/s390x/tcg-target-conset.h
@@ -21,6 +21,7 @@ C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, r)
C_O1_I2(v, v, r)
C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
C_O2_I2(b, a, 0, r)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index acea745016..afd90788c0 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -153,7 +153,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
/* used for function call generation */
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index ab53c8a05c..251287dd29 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -281,6 +281,7 @@ typedef enum S390Opcode {
VRRa_VUPH = 0xe7d7,
VRRa_VUPL = 0xe7d6,
VRRc_VX = 0xe76d,
+ VRRe_VSEL = 0xe78d,
VRRf_VLVGP = 0xe762,
VRSa_VERLL = 0xe733,
@@ -619,6 +620,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
}
+static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
+{
+ tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31);
+ tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31);
+ tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31);
+ tcg_debug_assert(v4 >= TCG_REG_V0 && v4 <= TCG_REG_V31);
+ tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15));
+ tcg_out16(s, v3 << 12);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | ((v4 & 15) << 12));
+}
+
static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
TCGReg v1, TCGReg r2, TCGReg r3)
{
@@ -2748,6 +2761,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
break;
+ case INDEX_op_bitsel_vec:
+ tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+ break;
+
case INDEX_op_cmp_vec:
switch ((TCGCond)args[3]) {
case TCG_COND_EQ:
@@ -2788,6 +2805,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_add_vec:
case INDEX_op_and_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_bitsel_vec:
case INDEX_op_neg_vec:
case INDEX_op_not_vec:
case INDEX_op_or_vec:
@@ -3129,6 +3147,8 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
return C_O1_I2(v, v, r);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(v, v, v, v);
default:
g_assert_not_reached();
--
2.25.1
next prev parent reply other threads:[~2020-12-25 20:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-25 20:19 [PATCH 00/16] tcg/s390x: host vector support Richard Henderson
2020-12-25 20:19 ` [PATCH 01/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2020-12-27 15:20 ` Philippe Mathieu-Daudé
2021-01-02 8:43 ` Thomas Huth
2020-12-25 20:19 ` [PATCH 02/16] tcg/s390x: Change FACILITY representation Richard Henderson
2020-12-27 15:25 ` Philippe Mathieu-Daudé
2020-12-25 20:19 ` [PATCH 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2020-12-27 15:25 ` Philippe Mathieu-Daudé
2020-12-25 20:19 ` [PATCH 04/16] tcg/s390x: Add host vector framework Richard Henderson
2020-12-25 20:19 ` [PATCH 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2020-12-25 20:19 ` [PATCH 06/16] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2020-12-25 20:19 ` [PATCH 07/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 08/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2020-12-25 20:19 ` [PATCH 09/16] tcg/s390x: Implement andc, orc, abs, neg, not " Richard Henderson
2020-12-25 20:19 ` [PATCH 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 11/16] tcg/s390x: Implement vector shift operations Richard Henderson
2020-12-25 20:19 ` [PATCH 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 13/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2020-12-25 20:19 ` [PATCH 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2020-12-25 20:19 ` Richard Henderson [this message]
2020-12-25 20:19 ` [PATCH 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201225201956.692861-16-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.