From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 06/16] tcg/s390x: Implement tcg_out_mov for vector types
Date: Fri, 25 Dec 2020 12:19:46 -0800 [thread overview]
Message-ID: <20201225201956.692861-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201225201956.692861-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++---
1 file changed, 68 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index bae70b9119..50113dbdd7 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -250,6 +250,11 @@ typedef enum S390Opcode {
RX_STC = 0x42,
RX_STH = 0x40,
+ VRRa_VLR = 0xe756,
+
+ VRSb_VLVG = 0xe722,
+ VRSc_VLGV = 0xe721,
+
VRX_VL = 0xe706,
VRX_VLLEZ = 0xe704,
VRX_VST = 0xe70e,
@@ -530,6 +535,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
| ((v4 & 16) << (4 - 3));
}
+static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, int m3)
+{
+ tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31);
+ tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31);
+ tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15));
+ tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
+}
+
+static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
+ intptr_t d2, TCGReg b2, TCGReg r3, int m4)
+{
+ tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31);
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(b2 <= TCG_REG_R15);
+ tcg_debug_assert(r3 <= TCG_REG_R15);
+ tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r3);
+ tcg_out16(s, b2 << 12 | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
+ intptr_t d2, TCGReg b2, TCGReg v3, int m4)
+{
+ tcg_debug_assert(r1 <= TCG_REG_R15);
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(b2 <= TCG_REG_R15);
+ tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31);
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 15));
+ tcg_out16(s, b2 << 12 | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
+}
+
static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
TCGReg b2, TCGReg x2, intptr_t d2, int m3)
{
@@ -563,12 +601,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
{
- if (src != dst) {
- if (type == TCG_TYPE_I32) {
+ if (src == dst) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (likely(dst < 16 && src < 16)) {
tcg_out_insn(s, RR, LR, dst, src);
- } else {
- tcg_out_insn(s, RRE, LGR, dst, src);
+ break;
}
+ /* fallthru */
+
+ case TCG_TYPE_I64:
+ if (likely(dst < 16)) {
+ if (likely(src < 16)) {
+ tcg_out_insn(s, RRE, LGR, dst, src);
+ } else {
+ tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
+ }
+ break;
+ } else if (src < 16) {
+ tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_out_insn(s, VRRa, VLR, dst, src, 0);
+ break;
+
+ default:
+ g_assert_not_reached();
}
return true;
}
--
2.25.1
next prev parent reply other threads:[~2020-12-25 20:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-25 20:19 [PATCH 00/16] tcg/s390x: host vector support Richard Henderson
2020-12-25 20:19 ` [PATCH 01/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2020-12-27 15:20 ` Philippe Mathieu-Daudé
2021-01-02 8:43 ` Thomas Huth
2020-12-25 20:19 ` [PATCH 02/16] tcg/s390x: Change FACILITY representation Richard Henderson
2020-12-27 15:25 ` Philippe Mathieu-Daudé
2020-12-25 20:19 ` [PATCH 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2020-12-27 15:25 ` Philippe Mathieu-Daudé
2020-12-25 20:19 ` [PATCH 04/16] tcg/s390x: Add host vector framework Richard Henderson
2020-12-25 20:19 ` [PATCH 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2020-12-25 20:19 ` Richard Henderson [this message]
2020-12-25 20:19 ` [PATCH 07/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 08/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2020-12-25 20:19 ` [PATCH 09/16] tcg/s390x: Implement andc, orc, abs, neg, not " Richard Henderson
2020-12-25 20:19 ` [PATCH 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 11/16] tcg/s390x: Implement vector shift operations Richard Henderson
2020-12-25 20:19 ` [PATCH 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 13/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2020-12-25 20:19 ` [PATCH 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2020-12-25 20:19 ` [PATCH 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
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